Editing Pentium Pro (section)

===Caching===
Likely Pentium Pro's most noticeable addition was its on-package [[L2 cache]], which ranged from 256&nbsp;KB at introduction to 1&nbsp;MB in 1997. At the time, manufacturing technology did not feasibly allow a large L2 cache to be integrated into the processor core. Intel instead placed the L2 die(s) separately in the package which still allowed it to run at the same clock speed as the CPU core. Additionally, unlike most motherboard-based cache schemes that shared the main system bus with the CPU, the Pentium Pro's cache had its own [[back-side bus]] (called ''[[dual independent bus]]'' by Intel). Because of this, the CPU could read main memory and cache concurrently, greatly reducing a traditional bottleneck.<ref>{{cite magazine |title=Accelerated Graphics Port |magazine=[[Next Generation (magazine)|Next Generation]]|issue=37|publisher=[[Imagine Media]] |date=January 1998 |pages=94–96}}</ref> The cache was also "non-blocking", meaning that the processor could issue more than one cache request at a time (up to 4), reducing cache-miss penalties; an example of [[memory-level parallelism]] (MLP). These properties combined to produce an L2 cache that was immensely faster than the motherboard-based caches of older processors. This cache alone gave the CPU an advantage in input/output performance over older [[x86]] CPUs. In multiprocessor configurations, Pentium Pro's integrated cache skyrocketed performance in comparison to architectures which had each CPU sharing a central cache.

However, this far faster L2 cache did come with some complications. The Pentium Pro's "on-package cache" arrangement was unique. The processor and the cache were on separate dies in the same package and connected closely by a full-speed bus. The two or three dies had to be bonded together early in the production process, before testing was possible. This meant that a single, tiny flaw in either die made it necessary to discard the entire assembly, which was one of the reasons for the Pentium Pro's relatively low production yield and high cost. All versions of the chip were expensive, those with 1024&nbsp;KB being particularly so, since it required two 512&nbsp;KB cache dies as well as the processor die.