Editing Physical layer (section)

== PHY ==
[[File:Elitegroup 761GX-M754 - Realtek RTL8201CL-5493.jpg|thumb|RTL8201 Ethernet PHY chip]]

[[File:DP83825I smaller.png|thumb|Texas Instruments DP83825 – 3&nbsp;×&nbsp;3&nbsp;mm 3.3&nbsp;V PHY chip]]{{Redirects here|PHY}}
A '''PHY''', an abbreviation for ''physical layer'', is an [[electronic circuit]], usually implemented as an [[integrated circuit]], required to implement physical layer functions of the [[OSI model]] in a [[network interface controller]].

A PHY connects a [[link layer]] device (often called MAC as an acronym for [[medium access control]]) to a physical medium such as an [[optical fiber]] or [[copper cable]]. A PHY device typically includes both [[physical coding sublayer]] (PCS) and [[physical medium dependent]] (PMD) layer functionality.<ref>{{cite book|url=https://books.google.com/books?id=DRIryrLoxKkC&q=ethernet+PHY&pg=PA495 |title=Data Center Fundamentals |author1=Mauricio Arregoces |author2=Maurizio Portolani |year=2003 |isbn=9781587050237 |access-date=2015-11-18}}</ref>

''-PHY'' may also be used as a suffix to form a short name referencing a specific physical layer protocol, for example [[M-PHY]].  

Modular transceivers for [[fiber-optic communication]] (like the [[small form-factor pluggable transceiver|SFP]] family) complement a PHY chip and form the [[Physical medium dependent|PMD]] sublayer.

=== Ethernet physical transceiver ===
[[File:Micrel KS8721CL on mainboard of Surf@home II-7778.jpg|thumb|[[Ray Zinn|Micrel]] KS8721CL – 3.3&nbsp;V single power supply 10/100BASE-TX/FX MII physical layer transceiver]]

The '''Ethernet PHY''' is a component that operates at the physical layer of the [[OSI model|OSI network model]].  It implements the physical layer portion of the Ethernet. Its purpose is to provide analog signal physical access to the link. It is usually interfaced with a [[media-independent interface]] (MII) to a MAC chip in a [[microcontroller]] or another system that takes care of the higher layer functions. 

More specifically, the Ethernet PHY is a chip that implements the hardware send and receive function of Ethernet [[Data frame|frame]]s; it interfaces between the analog domain of [[Ethernet physical layer | Ethernet's line modulation]] and the digital domain of link-layer [[Media Independent Interface|packet signaling]].<ref>{{cite web|url=http://electronics.stackexchange.com/questions/75596/what-is-the-difference-between-phy-and-mac-chip |title=microcontroller - what is the difference between PHY and MAC chip - Electrical Engineering Stack Exchange |publisher=Electronics.stackexchange.com |date=2013-07-11 |access-date=2015-11-18}}</ref>  The PHY usually does not handle MAC addressing, as that is the [[data link layer|link layer]]'s job.  Similarly, [[Wake-on-LAN]] and [[Network booting|Boot ROM]] functionality is implemented in the [[network interface card]] (NIC), which may have PHY, MAC, and other functionality integrated into one chip or as separate chips.

Common Ethernet interfaces include fiber or two to four copper pairs for data communication. However, there now exists a new interface, called Single Pair Ethernet (SPE), which is able to utilize a single pair of copper wires while still communicating at the intended speeds. [[Texas Instruments]] DP83TD510E<ref>{{cite web |title=DP83TD510E Ultra Low Power 802.3cg 10Base-T1L 10M Single Pair Ethernet PHY |url=https://www.ti.com/lit/ds/symlink/dp83td510e.pdf?ts=1602524952891&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FDP83TD510E |website=Texas Instruments |access-date=12 October 2020}}</ref> is an example of a PHY which uses SPE.

Examples include the [[Microsemi]] SimpliPHY and SynchroPHY VSC82xx/84xx/85xx/86xx family, [[Marvell Technology Group|Marvell]] Alaska 88E1310/88E1310S/88E1318/88E1318S Gigabit Ethernet transceivers, Texas Instruments DP838xx family<ref>{{cite web |title=Ethernet PHYs |url=https://www.ti.com/interface/ethernet/phys/overview.html |website=Texas Instruments |access-date=12 October 2020}}</ref> and offerings from Intel<ref>[http://www.intel.com/content/dam/doc/brochure/ethernet-controllers-phys-brochure.pdf Intel PHY controllers brochure]</ref> and ICS.<ref>[http://netwinder.osuosl.org/pub/netwinder/docs/nw/PHY/1890.pdf osuosl.org - ICS1890 10Base-T/100Base-TX Integrated PHYceiver datasheet]</ref>

===Other applications===
* [[Wireless LAN]] or [[Wi-Fi]]: The PHY portion consists of the RF, mixed-signal and analog portions, that are often called transceivers, and the digital baseband portion that use [[digital signal processor]] (DSP) and communication algorithm processing, including [[channel code]]s. It is common that these PHY portions are integrated with the [[medium access control]] (MAC) layer in [[system-on-a-chip]] (SOC) implementations. Similar wireless applications include [[3G]]/[[4G]]/[[3GPP Long Term Evolution|LTE]]/[[5G]], [[WiMAX]] and [[Ultra-wideband|UWB]].
* [[Universal Serial Bus]] (USB): A PHY chip is integrated into most USB controllers in hosts or [[embedded system]]s and provides the bridge between the digital and modulated parts of the interface.
* IrDA: The [[Infrared Data Association]]'s (IrDA) specification includes an IrPHY specification for the physical layer of the data transport.
* [[Serial ATA]] (SATA): Serial ATA controllers use a PHY.