Editing Reconfigurable computing (section)

== High-performance computing ==
'''High-Performance Reconfigurable Computing''' (HPRC) is a [[computer architecture]] combining reconfigurable computing-based accelerators like [[field-programmable gate array]] with CPUs or [[Multi-core processor|multi-core]] [[Microprocessor|processors]].

The increase of logic in an FPGA has enabled larger and more complex algorithms to be programmed into the FPGA. The attachment of such an FPGA to a modern CPU over a high speed bus, like [[PCI Express|PCI express]], has enabled the configurable logic to act more like a [[coprocessor]] rather than a [[peripheral]]. This has brought reconfigurable computing into the [[high-performance computing]] sphere.

Furthermore, by replicating an algorithm on an FPGA or the use of a multiplicity of FPGAs has enabled reconfigurable [[SIMD]] systems to be produced where several computational devices can concurrently operate on different data, which is highly [[parallel computing]].

This heterogeneous systems technique is used in computing research and especially in [[supercomputing]].<ref name="Voros2009">N. Voros, R. Nikolaos, A. Rosti, M. Hübner (editors): Dynamic System Reconfiguration in Heterogeneous Platforms - The MORPHEUS Approach; Springer Verlag, 2009</ref>
A 2008 paper reported speed-up factors of more than 4 orders of magnitude and energy saving factors by up to almost 4 orders of magnitude.<ref name="Tarek2008">{{cite journal |title= The promise of high-performance reconfigurable computing |author=Tarek El-Ghazawi |journal= IEEE Computer |volume= 41 |number=2 |pages= 69–76 |date= February 2008 |doi= 10.1109/MC.2008.65 |display-authors=etal|citeseerx= 10.1.1.208.4031 |s2cid= 14469864 }}</ref>
Some supercomputer firms offer heterogeneous processing blocks including FPGAs as accelerators.{{citation needed |date= August 2011}}
One research area is the twin-paradigm programming tool flow productivity obtained for such heterogeneous systems.<ref name="Esam2009">{{cite journal |author1= Esam El-Araby |author2= Ivan Gonzalez |author3= Tarek El-Ghazawi |title=  Exploiting Partial Runtime Reconfiguration for High-Performance Reconfigurable Computing |journal= ACM Transactions on Reconfigurable Technology and Systems |volume= 1 |number= 4 |date= January 2009 |doi= 10.1145/1462586.1462590 |pages=1–23|s2cid= 10270587 }}</ref>

The US [[National Science Foundation]] has a center for high-performance reconfigurable computing (CHREC).<ref>{{cite web |title= NSF center for High-performance Reconfigurable Computing |work= official web site |url= http://www.chrec.org/ |access-date= August 19, 2011 }}</ref>
In April 2011 the fourth Many-core and Reconfigurable Supercomputing Conference was held in Europe.<ref>{{cite web |title=Many-Core and Reconfigurable Supercomputing Conference |year=2011 |work=official web site |url=http://www.mrsc2011.eu/ |archive-url=https://web.archive.org/web/20101012042408/http://www.mrsc2011.eu/  |archive-date=October 12, 2010 |access-date=August 19, 2011 }}</ref>

Commercial high-performance reconfigurable computing systems are beginning to emerge with the announcement of [[IBM]] integrating FPGAs with its [[IBM Power microprocessors]].<ref>
{{cite web 
| url = http://www.hpcwire.com/off-the-wire/altera-ibm-unveil-fpga-accelerated-power-systems/
| title = Altera and IBM Unveil FPGA-Accelerated POWER Systems 
|publisher= HPCwire 
|date= 2014-11-17 
|access-date = 2014-12-14}}
</ref>