Editing Systolic array (section)

==Detailed description==
A systolic array is composed of matrix-like rows of [[data processing unit]]s called cells. Data processing units (DPUs) are similar to [[central processing unit]]s (CPUs), (except for the usual lack of a [[program counter]],<ref>The Paracel GeneMatcher series of systolic array processors do have a [[program counter]]. More complicated algorithms are implemented as a series of simple steps, with shifts specified in the instructions.</ref> since operation is [[transport triggered architecture|transport-triggered]], i.e., by the arrival of a data object). Each cell shares the information with its neighbors immediately after processing. The systolic array is often rectangular where data flows across the array between neighbour [[data processing unit|DPU]]s, often with different data flowing in different directions. The data streams entering and leaving the ports of the array are generated by auto-sequencing memory units, ASMs. Each ASM includes a data [[Counter (digital)|counter]]. In [[embedded system]]s a data stream may also be input from and/or output to an external source.

An example of a systolic [[algorithm]] might be designed for [[matrix multiplication]]. One [[matrix (mathematics)|matrix]] is fed in a row at a time from the top of the array and is passed down the array, the other matrix is fed in a column at a time from the left hand side of the array and passes from left to right. Dummy values are then passed in until each processor has seen one whole row and one whole column. At this point, the result of the multiplication is stored in the array and can now be output a row or a column at a time, flowing down or across the array.<ref>{{Cite web|url=http://web.cecs.pdx.edu/~mperkows/temp/May22/0020.Matrix-multiplication-systolic.pdf|title=Systolic Array Matrix Multiplication}}</ref>

Systolic arrays are arrays of [[data processing unit|DPU]]s which are connected to a small number of nearest neighbour DPUs in a mesh-like topology. DPUs perform a sequence of operations on data that flows between them. Because the traditional systolic array synthesis methods have been practiced by algebraic algorithms, only uniform arrays with only linear pipes can be obtained, so that the architectures are the same in all DPUs. The consequence is, that only applications with regular data dependencies can be implemented on classical systolic arrays. Like [[Single instruction, multiple data|SIMD]] machines, clocked systolic arrays compute in "lock-step" with each processor undertaking alternate compute | communicate phases. But systolic arrays with asynchronous handshake between DPUs are called ''wavefront arrays''.
One well-known systolic array is Carnegie Mellon University's [[iWarp]] processor, which has been manufactured by Intel. An iWarp system has a linear array processor connected by data buses going in both directions.