Editing Translation lookaside buffer (section)

==Typical TLB==
These are typical performance levels of a TLB:<ref name="typical">{{Cite book|title=Computer Organization And Design. Hardware/Software interface. 4th edition |author=David A. Patterson |author2=John L. Hennessy |year=2009 |publisher=Morgan Kaufmann Publishers |location=Burlington, MA 01803, USA |isbn=978-0-12-374493-7 |page=503 }}</ref>
* Size: 12 bits – 4,096 entries <!-- this is wider, than in book -->
* Hit time: 0.5 – 1 clock cycle
* Miss penalty: 10 – 100 clock cycles<!-- upd to COaD H/S I 4th -->
* Miss rate: 0.01 – 1% (20–40% for sparse/graph applications)

The average effective memory cycle rate is defined as <math>m + (1-p)h + pm</math> cycles, where <math>m</math> is the number of cycles required for a memory read, <math>p</math> is the miss rate, and <math>h</math> is the hit time in cycles.
If a TLB hit takes 1 clock cycle, a miss takes 30 clock cycles, a memory read takes 30 clock cycles, and the miss rate is 1%, the effective memory cycle rate is an average of <math>30 + 0.99 \times 1 + 0.01 \times 30</math> (31.29 clock cycles per memory access).<ref>{{Cite web|date=2019-02-26|title=Translation Lookaside Buffer (TLB) in Paging|url=https://www.geeksforgeeks.org/translation-lookaside-buffer-tlb-in-paging/|access-date=2021-02-10|website=GeeksforGeeks|language=en-US}}</ref>