Editing VHDL (section)

==Design==
VHDL is generally used to write text models that describe a logic circuit. Such a model is processed by a synthesis program, only if it is part of the logic design. A simulation program is used to test the logic design using simulation models to represent the logic circuits that interface to the design. This collection of simulation models is commonly called a ''testbench''.

A VHDL simulator is typically an [[Event-driven architecture|event-driven]] simulator.<ref>{{cite web|title=ELEC3017 - Simulation|url=http://users.ecs.soton.ac.uk/mz/elec3017/vhdlsim.pdf |archive-url=https://web.archive.org/web/20170223213703/http://users.ecs.soton.ac.uk/mz/elec3017/vhdlsim.pdf |archive-date=2017-02-23 |url-status=live|publisher=University of Southampton|access-date=23 February 2017}}</ref> This means that each transaction is added to an event queue for a specific scheduled time. For example, if a signal assignment should occur after 1 nanosecond, the event is added to the queue for time +1ns. Zero delay is also allowed, but still needs to be scheduled: for these cases [[delta delay]] is used, which represent an infinitely small time step. The simulation alters between two modes: statement execution, where triggered statements are evaluated, and event processing, where events in the queue are processed.

VHDL has constructs to handle the [[parallel computing|parallelism]] inherent in hardware designs, but these constructs (''processes'') differ in syntax from the parallel constructs in Ada (''tasks''). Like Ada, VHDL is [[strongly typed]] and is [[Case sensitivity|not case sensitive]]. In order to directly represent operations which are common in hardware, there are many features of VHDL which are not found in Ada, such as an extended set of Boolean operators including '''nand''' and '''nor'''.

VHDL has file input and output capabilities, and can be used as a general-purpose language for text processing, but files are more commonly used by a simulation testbench for stimulus or verification data. There are some VHDL compilers which build executable binaries. In this case, it might be possible to use VHDL to write a ''testbench'' to verify the functionality of the design using files on the host computer to define stimuli, to interact with the user, and to compare results with those expected. However, most designers leave this job to the simulator.

It is relatively easy for an inexperienced developer to produce code that simulates successfully but that cannot be synthesized into a real device, or is too large to be practical. One particular pitfall is the accidental production of [[transparent latch]]es rather than [[Flip-flop (electronics)#D flip-flop|D-type flip-flops]] as storage elements.<ref>{{cite web|title=Why should I care about Transparent Latches?|url=http://www.doulos.com/knowhow/fpga/latches/|publisher=Doulos|access-date=22 December 2012}}</ref>

One can design hardware in a VHDL IDE (for FPGA implementation such as Xilinx ISE, Altera Quartus, Synopsys Synplify, or Mentor Graphics HDL Designer) to produce the [[Register-transfer level|RTL]] schematic of the desired circuit. After that, the generated schematic can be verified using simulation software which shows the waveforms of inputs and outputs of the circuit after generating the appropriate testbench. To generate an appropriate testbench for a particular circuit or VHDL code, the inputs have to be defined correctly. For example, for clock input, a loop process or an iterative statement is required.<ref>{{cite web|title=Clock Generation|url=http://www.doulos.com/knowhow/vhdl_designers_guide/tips/clock_generation/|publisher=Doulos|access-date=22 December 2012}}</ref>

A final point is that when a VHDL model is translated into the "gates and wires" that are mapped onto a programmable logic device such as a [[CPLD]] or [[FPGA]], then it is the actual hardware being configured, rather than the VHDL code being "executed" as if on some form of a processor chip.