Editing Very-large-scale integration (section)

== Difficulties ==

As microprocessors become more complex due to [[Moore's law|technology scaling]], microprocessor designers have encountered several challenges which force them to think beyond the design plane, and look ahead to post-silicon:

* '''Process variation''' – As [[photolithography]] techniques get closer to the fundamental laws of optics, achieving high accuracy in [[dopant|doping]] concentrations and etched wires is becoming more difficult and prone to errors due to variation. Designers now must simulate across multiple fabrication [[process corners]] before a chip is certified ready for production, or use system-level techniques for dealing with effects of variation.<ref>{{Cite book |last1=Wu |first1=Qiang |title=2020 China Semiconductor Technology International Conference (CSTIC) |last2=Li |first2=Yanli |last3=Yang |first3=Yushu |last4=Chen |first4=Shoumian |last5=Zhao |first5=Yuhang |date=2020-06-26 |publisher=IEEE |isbn=978-1-7281-6558-5 |pages=1–6 |chapter=The Law that Guides the Development of Photolithography Technology and the Methodology in the Design of Photolithographic Process |doi=10.1109/CSTIC49141.2020.9282436 |chapter-url=https://ieeexplore.ieee.org/document/9282436}}</ref><ref>{{Cite web |title=Exploring the Challenges of VLSI Design: Navigating Complexity for Success |url=https://insemitech.com/blogs/exploring-the-challenges-of-vlsi-design-navigating-complexity-for-success/ |access-date=2024-08-10 |website=InSemi Tech |language=en-US}}</ref>
* '''Stricter design rules''' – Due to lithography and etch issues with scaling, [[design rule checking]] for [[Integrated circuit layout|layout]] has become increasingly stringent. Designers must keep in mind an ever increasing list of rules when laying out custom circuits. The overhead for custom design is now reaching a tipping point, with many design houses opting to switch to [[electronic design automation]] (EDA) tools to automate their design process.<ref>{{Cite book |last1=Wang |first1=Laung-Terng |url=https://dl.acm.org/doi/10.5555/2843514 |title=Electronic Design Automation: Synthesis, Verification, and Test |last2=Chang |first2=Yao-Wen |last3=Cheng |first3=Kwang-Ting (Tim) |date=February 2009 |publisher=Morgan Kaufmann Publishers Inc. |isbn=978-0-08-092200-3 |location=San Francisco, CA, USA}}</ref>
* '''[[Design closure|Timing/design closure]]''' – As [[clock frequencies]] tend to scale up, designers are finding it more difficult to distribute and maintain low [[clock skew]] between these high frequency clocks across the entire chip. This has led to a rising interest in [[multicore]] and [[multiprocessor]] architectures, since an [[Amdahl's law|overall speedup]] can be obtained even with lower clock frequency by using the computational power of all the cores.<ref>{{Cite web |date=2024-06-23 |title=Clock Skew in STA |url=https://vlsiweb.com/clock-skew/ |access-date=2024-08-10 |language=en-GB}}</ref>
* '''First-pass success''' – As [[die (integrated circuit)|die]] sizes shrink (due to scaling), and [[Wafer (electronics)|wafer]] sizes go up (due to lower manufacturing costs), the number of dies per wafer increases, and the complexity of making suitable [[photomask]]s goes up rapidly.  A [[mask set]] for a modern technology can cost several million dollars. This non-recurring expense deters the old iterative philosophy involving several "spin-cycles" to find errors in silicon, and encourages first-pass silicon success. Several design philosophies have been developed to aid this new design flow, including design for manufacturing ([[design for manufacturability (IC)|DFM]]), design for test ([[Design for Test|DFT]]), and [[Design for X]].<ref>{{Cite journal |last=Rieger |first=Michael L. |date=2019-11-26 |title=Retrospective on VLSI value scaling and lithography |url=https://www.spiedigitallibrary.org/journals/journal-of-micro-nanolithography-mems-and-moems/volume-18/issue-04/040902/Retrospective-on-VLSI-value-scaling-and-lithography/10.1117/1.JMM.18.4.040902.full |journal=Journal of Micro/Nanolithography, MEMS, and MOEMS |volume=18 |issue=4 |page=040902 |bibcode=2019JMM&M..18d0902R |doi=10.1117/1.JMM.18.4.040902 |issn=1932-5150}}</ref>
* '''[[Electromigration]]'''