Editing X86 memory segmentation (section)

=== Detailed segmentation unit workflow ===
A logical address consists of a 16-bit segment selector (supplying 13+1 address bits) and a 16-bit offset. The segment selector must be located in one of the segment registers. That selector consists of a 2-bit Requested [[Privilege level|Privilege Level]] (RPL), a 1-bit Table Indicator (TI), and a 13-bit index.

When attempting address translation of a given logical address, the processor reads the 64-bit [[segment descriptor]] structure from either the [[Global Descriptor Table]] when TI=0 or the [[Local Descriptor Table]] when TI=1. It then performs the privilege check:
: max(CPL, RPL) ≤ DPL
where CPL is the current privilege level (found in the lower 2&nbsp;bits of the CS register), RPL is the requested privilege level from the segment selector, and DPL is the descriptor privilege level of the segment (found in the descriptor).  All privilege levels are integers in the range 0–3, where the lowest number corresponds to the highest privilege.

If the inequality is false, the processor generates a [[general protection fault|general protection (GP) fault]].  Otherwise, address translation continues.  The processor then takes the 16-bit offset and compares it against the segment limit specified in the segment descriptor.  If it is larger, a GP fault is generated.  Otherwise, the processor adds the 24-bit segment base, specified in descriptor, to the offset, creating a linear physical address.

The privilege check is done only when the segment register is loaded, because [[segment descriptor]]s are cached in hidden parts of the segment registers.{{Citation needed|date=July 2011|reason=Is this true on the 80286, or only on the 80386 and above?}}<ref name=Arch>"Intel 64 and IA-32 Architectures Software Developer's Manual", Volume 3, "System Programming Guide", published in 2011, Page "Vol. 3A 3-11", the book is written: "''Every segment register has a “visible” part and a “hidden” part. (The hidden part is sometimes referred to as a “descriptor cache” or a “shadow register.”) When a segment selector is loaded into the visible part of a segment register, the processor also loads the hidden part of the segment register with the base address, segment limit, and access control information from the segment descriptor pointed to by the segment selector. The information cached in the segment register (visible and hidden) allows the processor to translate addresses without taking extra bus cycles to read the base address and limit from the segment descriptor.''"</ref>