Editing PCI Express (section)

== References ==
{{reflist|1=30em|refs=
<ref name="pcie-basics">{{cite web |url = http://www.pcisig.com/developers/main/training_materials/get_document?doc_id=4e00a39acaa5c5a8ee44ebb07baba982e5972c67 |title = PCI Express Basics |date = 2007-08-21 |access-date = 2014-07-15 |author = Ravi Budruk |publisher = [[PCI-SIG]] |format = PDF |url-status = dead |archive-url = https://web.archive.org/web/20140715120034/http://www.pcisig.com/developers/main/training_materials/get_document?doc_id=4e00a39acaa5c5a8ee44ebb07baba982e5972c67 |archive-date = 2014-07-15}}</ref>
<ref name="howstuffworks1">{{cite web | url = http://computer.howstuffworks.com/pci-express.htm | work = How Stuff Works | title = How PCI Express Works | access-date = 2009-12-07 | url-status = live | archive-url = https://web.archive.org/web/20091203053924/http://computer.howstuffworks.com/pci-express.htm | archive-date = 2009-12-03 | date = 2005-08-17|first1=Tracy V. |last1=Wilson}}</ref>
<ref name="faq1">{{cite web |url = http://www.pcisig.com/news_room/faqs/faq_express/ |title = PCI Express Architecture Frequently Asked Questions |publisher = PCI-SIG |access-date = 23 November 2008 |url-status = dead |archive-url = https://web.archive.org/web/20081113163608/http://www.pcisig.com/news_room/faqs/faq_express/ |archive-date = 13 November 2008}}</ref>
<ref name="PCIe card 2">{{Citation | title = PCI Express Card Electromechanical Specification Revision 2.0}}</ref>
<ref name="CEM1.1">''PCI Express Card Electromechanical Specification Revision 1.1''</ref>
<ref name="JuErgh">{{cite web|title=Mini-Fit® PCI Express®* Wire to Board Connector System|url=https://www.molex.com/pdm_docs/ps/PS-45558-001-001.pdf|access-date=4 December 2020}}</ref>
<ref name="CEM3.0">''PCI Express Card Electromechanical Specification Revision 3.0''</ref>
<ref name="EeePC">{{cite web|url=http://beta.ivancover.com/wiki/index.php/Eee_PC_Research|title=Eee PC Research|type=wiki|work=ivc|access-date=26 October 2009|url-status=usurped|archive-url=https://web.archive.org/web/20100330035948/http://beta.ivancover.com/wiki/index.php/Eee_PC_Research|archive-date=30 March 2010}}</ref>
<ref name="pcie_cabling1.0">{{cite web| title = PCI Express External Cabling 1.0 Specification| access-date = 9 February 2007| url = http://www.pcisig.com/specifications/pciexpress/pcie_cabling1.0/| url-status = live| archive-url = https://web.archive.org/web/20070210055546/http://www.pcisig.com/specifications/pciexpress/pcie_cabling1.0/| archive-date = 10 February 2007}}</ref>
<ref name="PoRghEr">{{Citation | title = PCI SIG discusses M-PCIe oculink & 4th gen PCIe | date = 13 September 2013 | newspaper = The Register | place = [[United Kingdom|UK]] | url = https://www.theregister.co.uk/Print/2013/09/13/pci_sig_discusses_m_pcie_oculink_and_fourth_gen_pcie/ | url-status = live | archive-url = https://web.archive.org/web/20170629201006/http://www.theregister.co.uk/Print/2013/09/13/pci_sig_discusses_m_pcie_oculink_and_fourth_gen_pcie/ | archive-date = 29 June 2017}}</ref>
<ref name="faq4">{{cite web|url = http://www.pcisig.com/news_room/faqs/FAQ_PCI_Express_4.0/#EQ3|archive-url = https://web.archive.org/web/20140518224913/http://www.pcisig.com/news_room/faqs/FAQ_PCI_Express_4.0/#EQ3|title = PCI Express 4.0 Frequently Asked Questions|access-date = 2014-05-18|archive-date = 2014-05-18|publisher = PCI-SIG|work = pcisig.com}}</ref>
<ref name="PCIExpressPressRelease">{{cite press release | title = PCI Express Base 2.0 specification announced | publisher = [[PCI-SIG]] | date = 15 January 2007 | access-date = 9 February 2007 | url = http://www.pcisig.com/news_room/PCIe2_0_Spec_Release_FINAL2.pdf | url-status = dead | archive-url = https://web.archive.org/web/20070304101327/http://www.pcisig.com/news_room/PCIe2_0_Spec_Release_FINAL2.pdf | archive-date = 4 March 2007}} — note that in this press release the term ''aggregate bandwidth'' refers to the sum of incoming and outgoing bandwidth; using this terminology the aggregate bandwidth of full duplex 100BASE-TX is 200{{nbsp}}Mbit/s.</ref>
<ref name="extrmetech">{{Cite news |url= http://www.extremetech.com/article2/0,1697,2169018,00.asp |title= PCI Express 3.0 Bandwidth: 8.0 Gigatransfers/s |publisher= ExtremeTech |date= 9 August 2007 |access-date= 5 September 2007 |url-status= live |archive-url= https://web.archive.org/web/20071024140702/http://www.extremetech.com/article2/0,1697,2169018,00.asp |archive-date= 24 October 2007}}</ref>
<ref name="faq3">{{cite web | url = http://www.pcisig.com/news_room/faqs/pcie3.0_faq/#EQ2 | archive-url = https://web.archive.org/web/20140201172536/http://www.pcisig.com/news_room/faqs/pcie3.0_faq/#EQ2 | title = PCI Express 3.0 Frequently Asked Questions | access-date = 2014-05-01 | archive-date = 2014-02-01 | publisher = PCI-SIG | work = pcisig.com}}</ref>
<ref name="OCuLink2">{{cite web|url=https://www.connectortips.com/oculink-connectors-cables-support-new-pcie-standard/|archiveurl=https://web.archive.org/web/20170313215047/http://www.connectortips.com/oculink-connectors-cables-support-new-pcie-standard/|url-status=dead|title=OCuLink connectors and cables support new PCIe standard|archivedate=March 13, 2017|website=www.connectortips.com}}</ref>
<ref name="EE_4+5">{{cite magazine |url=http://www.eetimes.com/document.asp?doc_id=1330006 |title=PCIe 4.0 Heads to Fab, 5.0 to Lab |magazine=EE Times |date=2016-06-26 |access-date=2016-08-27 |url-status=live |archive-url=https://web.archive.org/web/20160828221858/http://www.eetimes.com/document.asp?doc_id=1330006 |archive-date=2016-08-28}}</ref>
<ref name="heise_idf_2016">{{cite web |url=http://www.heise.de/newsticker/meldung/IDF-PCIe-4-0-laeuft-PCIe-5-0-in-Arbeit-3297114.html |title=IDF: PCIe 4.0 läuft, PCIe 5.0 in Arbeit |language=de |website=[[Heise Online]] |date=2016-08-18 |access-date=2016-08-18 |url-status=live |archive-url=https://web.archive.org/web/20160819153631/http://www.heise.de/newsticker/meldung/IDF-PCIe-4-0-laeuft-PCIe-5-0-in-Arbeit-3297114.html |archive-date=2016-08-19}}</ref>
<ref name="TR_pcie4">{{cite news|last1=Born|first1=Eric|title=PCIe 4.0 specification finally out with 16 GT/s on tap|url=https://techreport.com/news/32064/pcie-4-0-specification-finally-out-with-16-gt-s-on-tap|access-date=8 June 2017|publisher=Tech Report|date=8 June 2017|url-status=live|archive-url=https://web.archive.org/web/20170608155216/http://techreport.com/news/32064/pcie-4-0-specification-finally-out-with-16-gt-s-on-tap|archive-date=8 June 2017}}</ref>
<ref name="PCIe5r09">{{cite web|url=http://pcisig.com/doubling-bandwidth-under-two-years-pci-express®-base-specification-revision-50-version-09-now|title=Doubling Bandwidth in Under Two Years: PCI Express® Base Specification Revision 5.0, Version 0.9 is Now Available to Members|website=pcisig.com|language=en|access-date=2018-12-12}}</ref>
<ref name="businesswire.com">{{cite web|url=https://www.businesswire.com/news/home/20190618005945/en/PCI-SIG%C2%AE-Announces-Upcoming-PCI-Express%C2%AE-6.0-Specification-to-Reach-64-GTs|title=PCI-SIG® Announces Upcoming PCI Express® 6.0 Specification to Reach 64 GT/s|date=June 18, 2019|website=www.businesswire.com}}</ref>
<ref name="PCIeFiber">{{cite web |url=http://www.cablinginstall.com/index/display/article-display/8876181966/articles/cabling-installation-maintenance/news/data-center/2011/6/plx-demo_shows_pcie.html |title=PLX demo shows PCIe over fiber as data center clustering interconnect |publisher=Penn Well |work=Cabling install |access-date=29 August 2012 }}{{Dead link|date=April 2025 |bot=InternetArchiveBot |fix-attempted=yes }}</ref>
<ref name="adnacoPCIe">{{cite web |url=http://www.adnaco.com/2011/09/03/new1 |date=2011-04-22 |title=Introduced second generation PCI Express Gen 2 over fiber optic systems |publisher=Adnaco |access-date=29 August 2012 |url-status=live |archive-url=https://web.archive.org/web/20121004094357/http://www.adnaco.com/2011/09/03/new1/ |archive-date=4 October 2012}}</ref>
<ref name="pipe_spec">{{cite web | title = PHY Interface for the PCI Express Architecture | edition = version 2.00 | access-date = 21 May 2008 | publisher = Intel | url = http://download.intel.com/technology/pciexpress/devnet/docs/pipe2_00.pdf | url-status = dead | archive-url = https://web.archive.org/web/20080317171752/http://download.intel.com/technology/pciexpress/devnet/docs/pipe2_00.pdf | archive-date = 17 March 2008}}</ref>
<ref name="pcie_schematics1">{{cite web | publisher = Interface bus | title = Mechanical Drawing for PCI Express Connector | access-date = 7 December 2007 | url = http://www.interfacebus.com/PCI-Express-Bus-PCIe-Description.html#d}}</ref>
<ref name="pcie_schematics2">{{cite web | url = http://portal.fciconnect.com/Comergent/fci/drawing/10018783.pdf | title = FCi schematic for PCIe connectors | publisher = FCI connect | access-date = 7 December 2007}}</ref>
<ref name="traffic_profile">{{cite book| url=https://books.google.com/books?id=Xp7-NKsJ8_sC&dq=frequent+enforced+acknowledgements/&pg=PA35| title=Computer Peripherals And Interfaces| year=2008| publisher=Technical Publications Pune| isbn=9788184313086| access-date=23 July 2009| url-status=live| archive-url=https://web.archive.org/web/20140225203956/http://www.google.com/books?id=Xp7-NKsJ8_sC&pg=PA35&dq=frequent+enforced+acknowledgements%2F| archive-date=25 February 2014}}</ref>
<ref name="s5NDG">{{cite book |chapter=PCI express and advanced switching: Evolutionary path to building next generation interconnects |pages=21–29 |doi=10.1109/CONECT.2003.1231473 |date=August 2003 |title=11th Symposium on High Performance Interconnects, 2003. Proceedings. |last1=Mayhew |first1=D. |last2=Krishnan |first2=V. |isbn=0-7695-2012-X |s2cid=7456382}}</ref>
<ref name="DQmzv">{{cite web | url=https://www.pcmag.com/encyclopedia/term/48998/pci-express | title=Definition of PCI Express|work = PCMag}}</ref>
<ref name="gf9Lm">{{cite web | publisher = Fedora project | url = http://ols.fedoraproject.org/OLS/Reprints-2007/zhang-Reprint.pdf | title = Enable PCI Express Advanced Error Reporting in the Kernel | work = Proceedings of the Linux Symposium | first1 = Yanmin | last1 = Zhang | first2 = T Long | last2 = Nguyen | date = June 2007 | url-status = dead | archive-url = https://web.archive.org/web/20160310074031/https://ols.fedoraproject.org/OLS/Reprints-2007/zhang-Reprint.pdf | archive-date = 2016-03-10 | access-date = 2012-05-08}}</ref>
<ref name="sxOen">https://www.hyperstone.com Flash Memory Form Factors – The Fundamentals of Reliable Flash Storage, Retrieved 19 April 2018</ref>
<ref name="4TrCr">{{Citation | title=PCI Express Base Specification, Revision 2.1. | chapter=4.2.4.9. Link Width and Lane Sequence Negotiation | date=4 March 2009}}</ref>
<ref name="2Nt8T">{{cite web | work = Interface bus | url = http://www.interfacebus.com/Design_Connector_PCI_Express.html | title = PCI Express Bus | access-date = 2010-06-12 | url-status = dead | archive-url = https://web.archive.org/web/20071208162241/http://www.interfacebus.com/Design_Connector_PCI_Express.html | archive-date = 2007-12-08}}</ref>
<ref name="Gchhw">32 lanes are defined by the ''PCIe Base Specification'' up to PCIe 5.0 but there's no card standard in the ''PCIe Card Electromechanical Specification'' and that lane number was never implemented.</ref>
<ref name="odC7t">{{cite web | url = http://zone.ni.com/devzone/cda/tut/p/id/3767 | title = PCI Express – An Overview of the PCI Express Standard | work = Developer Zone | publisher = National Instruments | date = 2009-08-13 | access-date = 2009-12-07 | url-status = dead | archive-url = https://web.archive.org/web/20100105163040/http://zone.ni.com/devzone/cda/tut/p/id/3767 | archive-date = 2010-01-05}}</ref>
<ref name="P7MD8">{{cite web |url=https://pcgearlab.com/motherboard/what-are-pcie-slots/ |title=What are PCIe Slots? |last=Qazi |first=Atif|website=PC Gear Lab |access-date=8 April 2020}}</ref>
<ref name="8AKZj">{{cite web |url=http://www.nvmexpress.org/blog/new-pcie-form-factor-enables-greater-pcie-ssd-adoption/ |date=12 June 2012 |title=New PCIe Form Factor Enables Greater PCIe SSD Adoption |work=NVM Express |url-status=live |archive-url=https://web.archive.org/web/20150906180730/http://www.nvmexpress.org/blog/new-pcie-form-factor-enables-greater-pcie-ssd-adoption/ |archive-date=6 September 2015}}</ref>
<ref name="c1yve">{{cite web |url=http://www.storagereview.com/memblaze_pblaze4_aic_nvme_ssd_review |date=21 December 2015 |title=Memblaze PBlaze4 AIC NVMe SSD Review |work=StorageReview}}</ref>
<ref name="j6TTS">{{cite web|url=https://www.techradar.com/news/gaming/19-graphics-cards-that-shaped-the-future-of-gaming-1289666|title=19 graphics cards that shaped the future of gaming|first=Kane|last=Fulton|website=TechRadar|date=20 July 2015 }}</ref>
<ref name="RAreG">{{cite web|url=https://www.eurogamer.net/articles/digitalfoundry-2020-nvidia-geforce-rtx-3080-review|title=Nvidia GeForce RTX 3080 review: welcome to the next level|first=Richard|last=Leadbetter|website=[[Eurogamer]]|date=September 16, 2020}}</ref>
<ref name="E0Tsg">{{cite web|url=https://bit-tech.net/reviews/tech/graphics/sapphire-radeon-rx-5700-xt-pulse-review/1/|title=Sapphire Radeon RX 5700 XT Pulse Review {{!}} bit-tech.net|website=bit-tech.net|language=en|access-date=2019-08-26}}</ref>
<ref name="mAt96">{{cite web|url=http://xfxforce.com/en-gb/Products/product-category/amd-radeon-rx-5700xt-8gb-thicc-ii-rx-57xt8dfd6|title=AMD Radeon™ RX 5700 XT 8GB GDDR6 THICC II – RX-57XT8DFD6|website=xfxforce.com|access-date=2019-08-25|archive-date=1 September 2019|archive-url=https://web.archive.org/web/20190901193735/http://xfxforce.com/en-gb/Products/product-category/amd-radeon-rx-5700xt-8gb-thicc-ii-rx-57xt8dfd6|url-status=dead}}</ref>
<ref name="kk3xz">{{cite web|url=https://rog.asus.com/graphics-cards/graphics-cards/rog-strix/rog-strix-rtx3080-o10g-gaming-model/spec|title=ROG Strix GeForce RTX 3080 OC Edition 10GB GDDR6X &#124; Graphics Cards|website=rog.asus.com}}</ref>
<ref name="IM1RH">{{cite web| title=What is the A side, B side configuration of PCI cards| work=Frequently Asked Questions| publisher=Adex Electronics| year=1998| url=http://www.adexelec.com/faq.htm#pcikeys| access-date=24 October 2011| url-status=dead| archive-url=https://web.archive.org/web/20111102042843/http://www.adexelec.com/faq.htm#pcikeys| archive-date=2 November 2011}}</ref>
<ref name="ajnim">{{cite web | title = PCI Express Card Electromechanical Specification Revision 4.0, Version 1.0 (Clean)| url = https://members.pcisig.com/wg/PCI-SIG/document/13446}}</ref>
<ref name="vj2hg">{{cite web | url = https://pcisig.com/sites/default/files/specification_documents/ECN_L1_PM_Substates_with_CLKREQ_31_May_2013_Rev10a.pdf | title = L1 PM Substates with CLKREQ, Revision 1.0a | publisher = PCI-SIG | archive-url = https://web.archive.org/web/20181204125124/http://pcisig.com/sites/default/files/specification_documents/ECN_L1_PM_Substates_with_CLKREQ_31_May_2013_Rev10a.pdf | archive-date = 2018-12-04 | access-date = 2018-11-08}}</ref>
<ref name="YpQVq">{{cite web | url = https://pcisig.com/sites/default/files/specification_documents/Emergency%20Power%20Reduction%20Mechanism%20with%20PWRBRK%20Signal%20ECN.pdf | title = Emergency Power Reduction Mechanism with PWRBRK Signal ECN | publisher = PCI-SIG | archive-url = https://web.archive.org/web/20181109193739/https://pcisig.com/sites/default/files/specification_documents/Emergency%20Power%20Reduction%20Mechanism%20with%20PWRBRK%20Signal%20ECN.pdf | access-date = 2018-11-08| archive-date = 9 November 2018}}</ref>
<ref name="jArAO">{{Citation |publisher=PCI-SIG |first=Zale |last=Schoenborn |title=Board Design Guidelines for PCI Express Architecture |year=2004 |pages=19–21 |url=http://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/639/7851.PCIe_5F00_designGuides.pdf#page=19 |url-status=live |archive-url=https://web.archive.org/web/20160327185412/http://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/639/7851.PCIe_5F00_designGuides.pdf#page=19 |archive-date=2016-03-27}}</ref>
<ref name="o2GFI">''PCI Express x16 Graphics 150W-ATX Specification Revision 1.0''</ref>
<ref name="uLc7Q">''PCI Express 225 W/300 W High Power Card Electromechanical Specification Revision 1.0''</ref>
<ref name="mcd6L">{{cite web |url=http://kavi.pcisig.com/developers/main/training_materials/get_document?doc_id=fa4ec3357012d69821baa0856011c665ac770768 |title=PCIe Electromechanical Updates |author=Yun Ling |date=2008-05-16 |access-date=2015-11-07 |url-status=dead |archive-url=https://web.archive.org/web/20151105083550/http://kavi.pcisig.com/developers/main/training_materials/get_document?doc_id=fa4ec3357012d69821baa0856011c665ac770768 |archive-date=2015-11-05}}</ref>
<ref name="DmwJz">{{cite web |url = http://www.hwtools.net/Adapter/MP1.html |title = MP1: Mini PCI Express / PCI Express Adapter |date = 2014-07-18 |access-date = 2014-09-28 |website = hwtools.net |url-status = live |archive-url = https://web.archive.org/web/20141003233055/http://www.hwtools.net/Adapter/MP1.html |archive-date = 2014-10-03}}</ref>
<ref name="5xxpo">{{cite news | url = http://forum.notebookreview.com/lenovo-ibm/574993-msata-faq-basic-primer.html | title = mSATA FAQ: A Basic Primer | publisher = Notebook review | url-status = live | archive-url = https://web.archive.org/web/20120212164949/http://forum.notebookreview.com/lenovo-ibm/574993-msata-faq-basic-primer.html | archive-date = 2012-02-12}}</ref>
<ref name="xpI66">{{cite web |url = http://www.intel.com/support/motherboards/desktop/sb/CS-032415.htm?wapkw=032415 |publisher = [[Intel]] |title = Desktop Board Solid-state drive (SSD) compatibility |url-status = live |archive-url = https://web.archive.org/web/20160102233130/http://www.intel.com/support/motherboards/desktop/sb/CS-032415.htm?wapkw=032415 |archive-date = 2016-01-02}}</ref>
<ref name="oL68r">{{cite web|url=https://www.dell.com/support/article/en-us/sln301626/how-to-distinguish-the-differences-between-m-2-cards?lang=en|title=How to distinguish the differences between M.2 cards {{!}} Dell US|website=www.dell.com|access-date=2020-03-24}}</ref>
<ref name="ZTXPi">{{cite web |url=http://www.pcisig.com/news_room/news/press_release/02_07_07 |title=PCI Express External Cabling Specification Completed by PCI-SIG |publisher=PCI SIG |date=2007-02-07 |access-date=2012-12-07 |url-status=dead |archive-url=https://web.archive.org/web/20131126064157/http://www.pcisig.com/news_room/news/press_release/02_07_07 |archive-date=2013-11-26}}</ref>
<ref name="6MiK5">{{cite web|last=Mokosiy|first=Vitaliy|date=2020-10-09|title=Untangling terms: M.2, NVMe, USB-C, SAS, PCIe, U.2, OCuLink|url=https://mokosiy.medium.com/untangling-terms-m-2-nvme-usb-c-sas-pcie-6599c044f38e|access-date=2021-03-26|website=Medium|language=en}}</ref>
<ref name="tNP5L">{{cite web |url=http://www.supermicro.com/products/nfo/uio.cfm |title=Supermicro Universal I/O (UIO) Solutions |publisher=Supermicro.com |access-date=2014-03-24 |url-status=live |archive-url=https://web.archive.org/web/20140324184437/http://www.supermicro.com/products/nfo/uio.cfm |archive-date=2014-03-24}}</ref>
<ref name="osiit">{{Citation | contribution-url = http://www.edn.com/design/pc-board/4423319/Get-ready-for-M-PCIe-testing | contribution = Get ready for M-PCIe testing | publisher = EDN | title = PC board design}}</ref>
<ref name="HroAC">{{cite web |url= http://www.tmworld.com/electronics-news/4380071/What-does-GT-s-mean-anyway- |title= What does GT/s mean, anyway? |work= TM World |access-date= 2012-12-07 |url-status= live |archive-url= https://web.archive.org/web/20120814002641/http://www.tmworld.com/electronics-news/4380071/What-does-GT-s-mean-anyway- |archive-date= 2012-08-14}}</ref>
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<ref name="n9qGs">{{Citation | url = http://www.pcisig.com/ | title = PCI SIG | url-status = live | archive-url = https://web.archive.org/web/20080706134414/http://pcisig.com/ | archive-date = 2008-07-06}}</ref>
<ref name="UaYlc">{{cite web | first = Tony | last = Smith | website = The Register | title = PCI Express 2.0 final draft spec published | date = 11 October 2006 | access-date = 9 February 2007 | url = http://www.reghardware.co.uk/2006/10/11/pic-sig_posts_pcie_2_final_draft/ | url-status = live | archive-url = https://web.archive.org/web/20070129121731/http://www.reghardware.co.uk/2006/10/11/pic-sig_posts_pcie_2_final_draft/ | archive-date = 29 January 2007}}</ref>
<ref name="wHHTf">{{Cite news | first1 = Gary | last1 = Key | first2 = Wesley | last2 = Fink | publisher = [[AnandTech]] | title = Intel P35: Intel's Mainstream Chipset Grows Up | date = 21 May 2007 | access-date = 21 May 2007 | url = http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2993 | url-status = live | archive-url = https://web.archive.org/web/20070523055011/http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2993 | archive-date = 23 May 2007}}</ref>
<ref name="gL2GQ">{{Cite news | first = Anh | last = Huynh | publisher = [[AnandTech]] | title = NVIDIA "MCP72" Details Unveiled | date = 8 February 2007 | access-date = 9 February 2007 | url = http://www.dailytech.com/article.aspx?newsid=6021 | url-status = dead | archive-url = https://web.archive.org/web/20070210200616/http://www.dailytech.com/article.aspx?newsid=6021 | archive-date = 10 February 2007}}</ref>
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<ref name="iPAaS">''PCI Express Base Specification, Revision 3.0'' Table 4-24</ref>
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}}