Editing Ternary conditional operator (section)

===Verilog===
[[Verilog]] is technically a [[hardware description language]], not a programming language though the semantics of both are very similar. It uses the {{code|?:}} syntax for the ternary operator.

<syntaxhighlight lang="verilog">
// using blocking assignment
wire out;
assign out = sel ? a : b;
</syntaxhighlight>

This is equivalent to the more verbose Verilog code:

<syntaxhighlight lang="verilog">
// using blocking assignment
wire out;
if (sel === 1)  // sel is 1, not 0, x or z
    assign out = a;
else if (sel === 0)  // sel is 0, x or z (1 checked above)
    assign out = b;
else  // sel is x or z (0 and 1 checked above)
    assign out = [comment];  // a and b are compared bit by bit, and return for each bit
                             // an x if bits are different, and the bit value if the same
</syntaxhighlight>