Editing 555 timer IC (section)

== Modes ==
The 555 IC has the following operating modes:
# [[Multivibrator#Astable|Astable]] (free-running) mode – The 555 operates as an [[electronic oscillator]]. Applications include:
#* [[Light emitting diode]] and lamp flashers, [[Pulse generator|pulse generation]], [[pulse-width modulation]] (PWM), logic clocks, tone generation, security alarms, [[pulse-position modulation]], etc.
#* [[Analog-to-digital converter|Analog-to-digital conversion]] (ADC) from an analog value represented by a resistance or capacitance into a digital pulse length.
#** e.g., selecting a [[thermistor]] as timing resistor allows the use of the 555 in a [[temperature sensor]] with the period of the output pulse determined by the [[temperature]]. A microprocessor can then convert the pulse period to temperature, linearize it, and even provide calibration.
# [[Multivibrator#Monostable|Monostable]] (one-shot) mode – The 555 operates as a "one-shot" [[pulse generator]]. Applications include:
#* timers, missing pulse detection, bounce-free switches, touch switches, frequency dividers, triggered measurement of resistance or capacitance, PWM, etc.
# [[Multivibrator#Bistable|Bistable]] (latch) mode – The 555 operates as a [[Set-Reset latch|set-reset latch]]. Applications include:
#* [[Debouncing|switch debouncing]].
# [[Schmitt trigger]] (inverter) mode – the 555 operates as a Schmitt trigger [[Inverter (logic gate)|inverter gate]]. Application:
#* Converts a noisy input into a clean digital output.

=== Astable ===
{{stack|[[File:555 Astable Diagram.svg|thumb|Schematic of a 555 timer in astable mode]]}}
{{stack|[[File:NE555 Astable Waveforms.svg|thumb|Waveform in astable mode]]}}
{{see also|Electronic oscillator}}
{| class="wikitable floatright" style="text-align: right"
|-
|+ Astable mode examples with [[E series of preferred numbers|common values]]
! [[Frequency]] !! [[Capacitance|C]] !! [[Electrical resistance and conductance|R<sub>1</sub>]] !! R<sub>2</sub> !! [[Duty cycle]]
|-
| 0.1{{nbsp}}Hz (+0.048%) || 100{{nbsp}}μF || 8.2{{nbsp}}kΩ || 68{{nbsp}}kΩ || 52.8%
|-
| 1{{nbsp}}Hz (+0.048%) || 10{{nbsp}}μF || 8.2{{nbsp}}kΩ || 68{{nbsp}}kΩ || 52.8%
|-
| 10{{nbsp}}Hz (+0.048%) || 1{{nbsp}}μF || 8.2{{nbsp}}kΩ || 68{{nbsp}}kΩ || 52.8%
|-
| 100{{nbsp}}Hz (+0.048%) || 100{{nbsp}}nF || 8.2{{nbsp}}kΩ || 68{{nbsp}}kΩ || 52.8%
|-
| 1{{nbsp}}kHz (+0.048%) || 10{{nbsp}}nF || 8.2{{nbsp}}kΩ || 68{{nbsp}}kΩ || 52.8%
|-
| 10{{nbsp}}kHz (+0.048%) || 1{{nbsp}}nF || 8.2{{nbsp}}kΩ || 68{{nbsp}}kΩ || 52.8%
|-
| 100{{nbsp}}kHz (+0.048%) || 100{{nbsp}}pF || 8.2{{nbsp}}kΩ || 68{{nbsp}}kΩ || 52.8%
|}<!-- NOTE: Common preferred values are best for examples. Capacitors are E3 series values, resistors are E6 or E12 series values. user:sbmeirow -->

In the astable configuration, the 555 timer puts out a continuous stream of rectangular pulses having a specific period.

The astable configuration is implemented using two resistors, <math>R_1</math> and <math>R_2 ,</math> and one capacitor <math>C</math>. The threshold and trigger pins are both connected to the capacitor; thus they have the same voltage.

Its repeated operating cycle (starting with the capacitor uncharged) is:

# Since the capacitor's voltage will be below {{Frac|1|3}}&nbsp;''V''<sub>CC</sub>, the trigger pin causes the 555's internal latch to change state, causing OUT to go high and the internal discharge transistor to cut-off.
# Since the discharge pin is no longer short-circuited to ground, the capacitor starts charging via current from Vcc through the resistors <math>R_1</math> and <math>R_2</math>.
# Once the capacitor charge reaches {{Frac|2|3}}&nbsp;Vcc, the threshold pin causes the 555's internal latch to change state, causing OUT to go low and the internal discharge transistor to go into saturation (maximal-conductivity) mode.
# This discharge transistor provides a discharge path, so the capacitor starts discharging through <math>R_2</math>.
# Once the capacitor's voltage drops below {{Frac|1|3}}&nbsp;''V''<sub>CC</sub>, the cycle repeats from step 1.

During the first pulse, the capacitor charges from 0&nbsp;V to {{Frac|2|3}}&nbsp;''V''<sub>CC</sub>, however, in later pulses, it only charges from {{Frac|1|3}}&nbsp;''V''<sub>CC</sub> to {{Frac|2|3}}&nbsp;''V''<sub>CC</sub>. Consequently, the first pulse has a longer high time interval compared to later pulses. Moreover, the capacitor charges through both resistors but only discharges through <math>R_2</math>, thus the output high interval is longer than the low interval. This is shown in the following equations:

The output high time interval of each pulse is given by:<ref name="Signetics_1973_555-556_Databook"/>

: <math>t_\text{high} = \ln(2) \cdot (R_1 + R_2) \cdot C</math>

The output low time interval of each pulse is given by:<ref name="Signetics_1973_555-556_Databook"/>

: <math>t_\text{low} = \ln(2) \cdot R_2 \cdot C</math>

Hence, the [[frequency]] <math>f</math> of the pulse is given by:<ref name="Signetics_1973_555-556_Databook"/>

: <math>f = \frac{1}{t_\text{high} + t_\text{low}} = \frac{1}{\ln(2) \cdot (R_1 + 2 \, R_2) \cdot C}</math>

and the [[duty cycle]] <math>D</math> is given by:<ref name="Signetics_1973_555-556_Databook"/>

: <math>D~(\%) = \frac{t_\text{high}}{t_\text{high} + t_\text{low}} \cdot 100 = \frac{R_1 + R_2}{R_1 + 2 \, R_2} \cdot 100</math>

where <math>t</math> is the time in [[second]]s, <math>R</math> is the resistance in [[ohm]]s, <math>C</math> is the capacitance in [[farad]]s, and <math>\ln(2)</math> is the [[natural logarithm of 2|natural log of 2]] constant.{{Efn|[[natural logarithm of 2|ln(2)]] is a constant, approximately 0.693147 (rounded to 6 significant digits), or commonly rounded to fewer digits in 555 timer books and datasheets to 0.693, 0.69, or 0.7}}

[[File:555 Mk-sp Diagram.svg|thumb|right|Schematic of a 555 timer in astable mode with a 1N4148 diode to create a duty cycles less than 50%]]
Resistor <math>R_1</math> requirements:
* The maximum current through <math>R_1</math> must be lower than the maximum current rating of the internal transisor at the DISCHARGE pin, because this transistor "shorts" the DISCHARGE pin to the GND pin (per internal schematics above) to drain the capacitor.  This is the reason why <math>R_1</math> shouldn't be a very low resistance, such as when a variable [[Trimmer (electronics)|trimmer]] or [[potentiometer]] is used instead of a fixed value resistor.
* The maximum power rating of <math>R_1</math> must be greater than <math>\frac{{V_\text{CC}}^2}{R_1}</math>, per [[Ohm's law]].

==== Shorter duty cycle ====
To create an output high time shorter than the low time (i.e., a [[duty cycle]] less than 50%) a fast diode (i.e. [[1N4148 signal diode]]) can be placed in parallel with R<sub>2</sub>, with the cathode on the capacitor side.<ref name="Signetics_1973_555-556_Databook"/> This bypasses R<sub>2</sub> during the high part of the cycle, so that the high interval depends only on R<sub>1</sub> and C, with an adjustment based on the voltage drop across the diode. The low time is unaffected by the diode and so remains <math display="inline">\ln(2) \, R_2 \, C \, .</math> But the diode's forward [[voltage drop]] ''V''<sub>diode</sub> slows charging on the capacitor, so the high time is longer than the often-cited <math display="inline">\ln(2) \, R_1 \, C</math> to become:

: <math>t_\text{high} = \ln\left(\frac{2 \, V_\text{CC} - 3 \, V_\text{diode}}{V_\text{CC} - 3 \, V_\text{diode}}\right) \cdot R_1 \cdot C,</math>

where ''V''<sub>diode</sub> is when the diode's "on" current is {{Frac|1|2}} of ''V''<sub>CC</sub>/R<sub>1</sub> (which [[Diode forward voltage drop|depends on the type of diode]] and can be found in datasheets or measured). When V<sub>diode</sub> is small relative to ''V''<sub>cc</sub>, this charging is faster and approaches <math display="inline">\ln(2) \, R_1 \, C</math> but is slower the closer V<sub>diode</sub> is to ''V''<sub>cc</sub>:

<blockquote>As an extreme example, when ''V''<sub>CC</sub> = 5&nbsp;V, and V<sub>diode</sub> = 0.7&nbsp;V, high time is 1.00&nbsp;R<sub>1</sub>C, which is 45% longer than the "expected" 0.693&nbsp;R<sub>1</sub>C. At the other extreme, when ''V''<sub>cc</sub> = 15&nbsp;V, and V<sub>diode</sub> = 0.3&nbsp;V, the high time is 0.725&nbsp;R<sub>1</sub>C, which is closer to the expected 0.693&nbsp;R<sub>1</sub>C. The equation approaches 0.693&nbsp;R<sub>1</sub>C as ''V''<sub>diode</sub> approaches 0&nbsp;V.</blockquote>

==== Voltage-controlled pulse-width modulation ====
In the previous example schematics, the control pin was not used, thus it should connected to ground through a 10&nbsp;[[Farad|nF]] [[decoupling capacitor]] to shunt electrical noise. However, if a time-varying voltage source was applied to the control pin, then the pulse widths would be dependent on the control voltage.

=== Monostable ===
{{stack|[[File:555 Monostable.svg|thumb|Schematic of a 555 in monostable mode. Example values C = 100&nbsp;nF, R = 180&nbsp;kΩ to 220&nbsp;kΩ for debouncing a pulled-up pushbutton.]]}}
{{stack|[[File:NE555 Monotable Waveforms (English).png|thumb|Waveform in monostable mode]]}}
{{see also|RC circuit}}

Monostable mode produces an output pulse when the trigger signals drops below {{Frac|1|3}} ''V''<sub>CC</sub>. An [[RC circuit]] sets the output pulse's duration as the time <math>t</math> in [[second]]s it takes to charge C to {{Frac|2|3}} ''V''<sub>CC</sub>:<ref name="Signetics_1973_555-556_Databook" />

: <math>t = \ln(3) \cdot R \cdot C,</math>

where <math>R</math> is the resistance in [[ohm]]s, <math>C</math> is the capacitance in [[farad]]s, <math>\ln(3)</math> is the [[Natural logarithm|natural log]] of 3 constant.{{efn|[[Natural logarithm|ln(3)]] is a constant, approximately 1.098612 (rounded to 6 significant digits), or commonly rounded to fewer digits in 555 timer books and datasheets to 1.099 or 1.1}}  The output pulse duration can be lengthened or shortened as desired by adjusting the values of R and C. Subsequent triggering before the end of this timing interval won't affect the output pulse.<ref name="TI_LM555_Datasheet" />

==== Example values ====
{| class="wikitable floatright" style="text-align: right"
|-
|+ Monostable mode examples with [[E series of preferred numbers|common values]]
! [[Second|Time]] !! [[Farad|C]] !! [[Ohm|R]]
|-
| 100 μs (−0.026%) || 1 nF || 91 kΩ
|-
| 1 ms (−0.026%) || 10 nF || 91 kΩ
|-
| 10 ms (−0.026%) || 100 nF || 91 kΩ
|-
| 100 ms (−0.026%) || 1 μF || 91 kΩ
|-
| 1 s (−0.026%) || 10 μF || 91 kΩ
|-
| 10 s (−0.026%) || 100 μF || 91 kΩ
|}<!-- NOTE: Common preferred values are best for examples. Capacitors are E3 series values, resistors are E24 series values. user:sbmeirow -->

The timing table (right) shows common electronic component value solutions for various powers of 10 timings.

Scaling R and C by opposite powers of 10 will provide the same timing. For instance:<!-- NOTE: per [[Wikipedia:These are not original research#Simple calculations]], from user:sbmeirow -->
* 1{{nbsp}}ms [[≅]] 1{{nbsp}}nF and 910{{nbsp}}kΩ,
* '''1{{nbsp}}ms ≅ 10{{nbsp}}nF and 91{{nbsp}}kΩ (values from table)''',
* 1{{nbsp}}ms ≅ 100{{nbsp}}nF and 9.1{{nbsp}}kΩ.

For each row in the example table (right), additional timing values can easily be created by adding one to three of the same resistor value in parallel and/or series. A second resistor in parallel, the new timing is half the table time. A second resistor in series, the new timing is double the table time.<!-- NOTE: per [[Wikipedia:These are not original research#Simple calculations]], from user:sbmeirow -->
* 2.5{{nbsp}}ms (0.25x) [[≅]] 100{{nbsp}}nF and 22.75{{nbsp}}kΩ (four 91{{nbsp}}kΩ resistors in [[Series and parallel circuits|parallel]]),
* 5{{nbsp}}ms (0.5x)  ≅ 100{{nbsp}}nF and 45.5{{nbsp}}kΩ (two 91{{nbsp}}kΩ resistors in parallel),
* '''10{{nbsp}}ms (1x) ≅ 100{{nbsp}}nF and 91{{nbsp}}kΩ (values from table)''',
* 15{{nbsp}}ms (1.5x) ≅ 100{{nbsp}}nF and 136.5{{nbsp}}kΩ (one 91{{nbsp}}kΩ resistor in series with "two 91{{nbsp}}kΩ resistors in parallel"),
* 20{{nbsp}}ms (2x) ≅ 100{{nbsp}}nF and 182{{nbsp}}kΩ (two 91{{nbsp}}kΩ resistors in [[Series and parallel circuits|series]]),
* 25{{nbsp}}ms (2.5x) ≅ 100{{nbsp}}nF and 227.5{{nbsp}}kΩ ("two 91{{nbsp}}kΩ resistors in series" in series with "two 91{{nbsp}}kΩ resistors in parallel"),
* 30{{nbsp}}ms (3x) ≅ 100{{nbsp}}nF and 273{{nbsp}}kΩ (three 91{{nbsp}}kΩ resistors in series),
* 40{{nbsp}}ms (4x) ≅ 100{{nbsp}}nF and 364{{nbsp}}kΩ (four 91{{nbsp}}kΩ resistors in series).
{{clear}}

=== Bistable SR latch ===
{{stack|[[File:555 Bistabiel digitaal.svg|thumb|Schematic of a 555 in bistable [[SR latch]] mode]]}}{{stack|[[File:Inverted SR Flip-flop.svg|thumb|100px|[[Active-low]] [[SR latch]] symbol, but lacks /Q output]]}}<!-- NOTE: Need better version with /Q removed. user:sbmeirow -->

{{see also|Set-Reset latch}}

A 555 timer can act as an [[Active low|active-low]] [[Set-Reset latch|SR latch]] (though without an inverted {{overline|Q}} output) with two outputs: output pin is a [[Push–pull output|push-pull]] output, discharge pin is an [[open-collector]] output (requires a [[pull-up resistor]]).

For the schematic on the right, a {{overline|Reset}} input signal connects to the {{overline|RESET}} pin and connecting a {{overline|Set}} input signal to the {{overline|TR}} pin. Thus, pulling {{overline|Set}} momentarily low acts as a "set" and transitions the output to the high state (''V''<sub>CC</sub>). Conversely, pulling {{overline|Reset}} momentarily low acts as a "reset" and transitions the Out pin to the low state (GND).

No timing capacitors are required in a bistable configuration. The threshold input is grounded because it is unused.<ref>{{Cite book |last=Buiting |first=Jan |url=https://books.google.com/books?id=rZDbnQ0siCYC&q=555+pin+7+%22open+collector%22&pg=PA84 |title=308 Circuits |date=2003 |publisher=Elektor International Media |isbn=978-0-905705-66-8 |language=en}}</ref> The trigger and reset inputs may be held high via [[pull-up resistor]]s if they are normally [[Hi-Z]] and only enabled by connecting to ground.
{{clear}}

=== Bistable Schmitt trigger inverter gate ===
{{stack|[[File:555 Bistabiel analoog.svg|thumb|Schematic of a 555 timer in bistable Schmitt trigger inverter mode. Example values C = 100 nF, R1 & R2 = 100 kΩ.]]}}
{{stack|[[File:Inverting Schmitt trigger symbol.svg|thumb|125px|Schmitt trigger inverter symbol]]}}
{{see also|Inverter gate}}

A 555 timer can be used to create a [[Schmitt trigger]] [[Inverter (logic gate)|inverter gate]] with two outputs: output pin is a [[Push–pull output|push-pull]] output, discharge pin is an [[open-collector]] output (requires a [[pull-up resistor]]).

For the schematic on the right, an input signal is [[Capacitive coupling|AC-coupled]] through a low value series capacitor, then biased by identical high-resistance resistors <math>R_1</math> and <math>R_2</math>, which causes the signal to be centered at {{Frac|1|2}} ''V''<sub >cc</sub>.  This centered signal is connected to both the trigger and threshold input pins of the timer.  The input signal must be strong enough to excite the trigger levels of the comparators to exceed the lower {{Frac|1|3}} ''V''<sub>CC</sub> and upper {{Frac|2|3}} ''V''<sub>CC</sub> thresholds in order to cause them to change state, thus providing the Schmitt trigger feature.<ref>{{cite web |title=555 Timer as Schmitt Trigger |url=https://www.electronicshub.org/555-timer-as-schmitt-trigger/ |website=Electronics Hub |archive-url=https://web.archive.org/web/20230315063926/https://www.electronicshub.org/555-timer-as-schmitt-trigger/ |archive-date=March 15, 2023 |date=June 19, 2015 |url-status=live}}</ref>

No timing capacitors are required in a bistable configuration.
{{clear}}