Editing ARM architecture family (section)

===ARM2===
The result of the simulations on the ARM1 boards led to the late 1986 introduction of the ARM2 design running at 8&nbsp;MHz, and the early 1987 speed-bumped version at 10 to 12&nbsp;MHz.{{efn|Matt Evans notes that it appears the faster versions were simply binned higher, and appear to have no underlying changes.{{sfn|Evans|2019|loc=22:00}}}} A significant change in the underlying architecture was the addition of a [[Booth's multiplication algorithm|Booth multiplier]], whereas formerly multiplication had to be carried out in software.{{sfn|Evans|2019|loc=21:30}} Further, a new Fast Interrupt reQuest mode, FIQ for short, allowed registers 8 through 14 to be replaced as part of the interrupt itself. This meant FIQ requests did not have to save out their registers, further speeding interrupts.{{sfn|Evans|2019|loc=22:0030}}

The first use of the ARM2 were in ARM Evaluations systems, supplied as a second processor for BBC Micro and Master machines, from July 1986,<ref>{{Cite web |title=Chris's Acorns: Acorn OEM Products |url=http://chrisacorns.computinghistory.org.uk/docs/Acorn/OEM/OEM.html |access-date=2025-04-24 |website=chrisacorns.computinghistory.org.uk}}</ref> internal Acorn A500 development machines,<ref>{{Cite web |title=Chris's Acorns: Acorn A500 (prototype) |url=http://chrisacorns.computinghistory.org.uk/Computers/A500.html |access-date=2025-04-24 |website=chrisacorns.computinghistory.org.uk}}</ref> and the [[Acorn Archimedes]] personal computer models A305, A310, and A440, launched on the 6th June 1987.

According to the [[Dhrystone]] benchmark, the ARM2 was roughly seven times the performance of a typical 7&nbsp;MHz 68000-based system like the [[Amiga]] or [[Macintosh SE]]. It was twice as fast as an [[i386|Intel 80386]] running at 16&nbsp;MHz, and about the same speed as a multi-processor [[VAX-11#VAX-11/784|VAX-11/784]] [[superminicomputer]]. The only systems that beat it were the [[Sun SPARC]] and [[R2000 microprocessor|MIPS R2000]] RISC-based [[workstation]]s.{{sfn|Evans|2019|loc=14:00}} Further, as the CPU was designed for high-speed I/O, it dispensed with many of the support chips seen in these machines; notably, it lacked any dedicated [[direct memory access]] (DMA) controller which was often found on workstations. The graphics system was also simplified based on the same set of underlying assumptions about memory and timing. The result was a dramatically simplified design, offering performance on par with expensive workstations but at a price point similar to contemporary desktops.{{sfn|Evans|2019|loc=14:00}}

The ARM2 featured a [[32-bit computing|32-bit]] [[Bus (computing)|data bus]], [[26-bit computing|26-bit]] address space and 27&nbsp;32-bit [[processor register|registers]], of which 16 are accessible at any one time (including the [[program counter|PC]]).<ref>{{cite web |url=https://www.cs.umd.edu/~meesh/cmsc411/website/proj01/arm/armchip.html |title=From one Arm to the next! ARM Processors and Architectures |access-date=31 May 2022}}</ref> The ARM2 had a [[transistor count]] of just 30,000,<ref name="Markus Levy, Convergence Promotions">{{cite web |url=https://reds.heig-vd.ch/share/cours/ReCo/documents/TheHistoryOfTheARMArchitecture.pdf |title=The History of The ARM Architecture: From Inception to IPO |access-date=18 July 2022 |last=Levy |first=Markus}}</ref> compared to Motorola's six-year-older 68000 model with around 68,000. Much of this simplicity came from the lack of [[microcode]], which represents about one-quarter to one-third of the 68000's transistors, and the lack of (like most CPUs of the day) a [[CPU cache|cache]]. This simplicity enabled the ARM2 to have a low power consumption and simpler thermal packaging by having fewer powered transistors. Nevertheless, ARM2 offered better performance than the contemporary 1987 [[IBM PS/2 Model 50]], which initially utilised an [[Intel 80286]], offering 1.8 MIPS @ 10&nbsp;MHz, and later in 1987, the 2 MIPS of the PS/2 70, with its [[i386|Intel 386]] DX @ 16&nbsp;MHz.<ref>{{Cite book |url=http://oldcomputers.net/Amiga_3000_manual.pdf |title=Introducing the Commodore Amiga 3000 |date=1991 |publisher=Commodore-Amiga, Inc.}}</ref><ref>{{Cite web |title=Computer MIPS and MFLOPS Speed Claims 1980 to 1996 |url=http://www.roylongbottom.org.uk/mips.htm#anchorAcorn |access-date=2023-06-17 |website=www.roylongbottom.org.uk}}</ref>

A successor, ARM3, was produced with a 4 KB cache, which further improved performance.<ref name="Chattopadhyay2010">{{cite book |author=Santanu Chattopadhyay |title=Embedded System Design |url=https://books.google.com/books?id=4Bir9Kw059gC&pg=PA9 |year=2010 |publisher=PHI Learning Pvt. Ltd. |isbn=978-81-203-4024-4 |page=9}}</ref> The address bus was extended to 32&nbsp;bits in the ARM6, but program code still had to lie within the first 64 MB of memory in 26-bit compatibility mode, due to the reserved bits for the status flags.<ref>{{cite web |url=https://www.heyrick.co.uk/assembler/32bit.html |title=32&nbsp;bit operation |author=Richard Murray}}</ref>