Editing Accellera (section)

==Standards==
The following EDA standards developed by Accellera were ratified by IEEE by 2019:<ref name=merger/>
*[[Verilog]] or IEEE 1364 or IEC 61691-4
*[[VHDL]] or IEEE 1076 or IEC 61691-1-1
*[[Property Specification Language]] (PSL) or IEEE 1850 or IEC 62531
*[[SystemC]] or IEEE 1666
*SystemC Analog/Mixed-Signal extensions or IEEE 1666.1
*[[SystemVerilog]] or IEEE 1800
*[[Standard Delay Format]] (SDF) or IEEE 1497 or IEC 61523-3
*Delay and Power Calculation System ([[DPCS]]/OLA; see [[Standard Parasitic Exchange Format]]) or IEEE 1481
*[[Advanced Library Format]] (ALF) or IEEE 1603 or IEC 62265
*[[Open Compression Interface]] (OCI) or IEEE 1450.6.1
*[[Unified Power Format]] (UPF) or IEEE 1801
*[[Open Model Interface]] (OMI) or IEEE 1499
*[[IP-XACT]] or IEEE 1685
*[[Universal Verification Methodology]] (UVM) or IEEE 1800.2

The following EDA initiatives were developed by Accellera:
*[[Open Core Protocol]] (OCP)
*[[Open Verification Language]] (OVL)
*[[Open Verification Library]]  (OVL)
*Portable Test & Stimulus Standard (PSS)
*[[Standard Co-Emulation-Modeling Interface]] (SCE-MI)
*[[Soft IP Tagging]]
*[[SystemRDL]] (System Register Description Language)
*[[Unified Coverage Interoperability Standard]] (UCIS)
*[[Universal Verification Methodology]] (UVM)
*[[Verilog-AMS]] (Analog Mixed-Signal)