Editing Adder (electronics) (section)

====Ripple-carry adder====
[[File:4-bit ripple carry adder.svg|thumb|4-bit adder with logical block diagram shown|alt=4-bit adder with logical block diagram shown]]
[[File:RippleCarry2.gif|thumb|Decimal 4-digit ripple carry adder. FA = full adder, HA = half adder.]]

It is possible to create a logical circuit using multiple full adders to add ''N''-bit numbers. Each full adder inputs a <math>C_{in}</math>, which is the <math>C_{out}</math> of the previous adder. This kind of adder is called a '''ripple-carry adder''' (RCA), since each carry bit "ripples" to the next full adder. The first (and only the first) full adder may be replaced by a half adder (under the assumption that <math>C_{in} = 0</math>).

The layout of a ripple-carry adder is simple, which allows fast design time; however, the ripple-carry adder is relatively slow, since each full adder must wait for the carry bit to be calculated from the previous full adder. The [[gate delay]] can easily be calculated by inspection of the full adder circuit. Each full adder requires three levels of logic. In a 32-bit ripple-carry adder, there are 32 full adders, so the critical path (worst case) delay is 3 (from input to <math>C_{out}</math> of first adder) + 31 × 2 (for carry propagation in latter adders) = 65 gate delays.<ref name="Adder"/>
The general equation for the worst-case delay for a ''n''-bit carry-ripple adder, accounting for both the sum and carry bits, is:

:<math>T_\text{CRA}(n) = T_\text{HA} + (n-1) \cdot T_\text{c} + T_\text{s} = </math><math> T_\text{FA} + (n-1) \cdot T_c = </math><math> 3 D + (n-1) \cdot 2 D = (2n+1) \cdot D</math>

A design with alternating carry polarities and optimized [[AND-OR-Invert]] gates can be about twice as fast.<ref name="Burgess_2011"/><ref name="Fischer">{{Cite web|url=https://sus.ziti.uni-heidelberg.de/Lehre/WS1617_DST/DST_Fischer_06_Einfache_Bloecke_FF.pptx.pdf|title=Einfache Schaltungsblöcke|accessdate=2021-09-05|archive-url=https://web.archive.org/web/20210905175605/https://sus.ziti.uni-heidelberg.de/Lehre/WS1617_DST/DST_Fischer_06_Einfache_Bloecke_FF.pptx.pdf|archive-date=2021-09-05|last=Fischer|first=P.|publisher=Universität Heidelberg}}</ref>