Editing Cell (processor) (section)

===Power Processor Element (PPE)===
{{Main | Power Processing Element}}
[[File:PPE (Cell).png|thumb|PPE]]
The ''PPE''<ref name="cc.gatech.edu">{{Cite web |last=Kim |first=Hyesoon |author-link=Hyesoon Kim |date=Spring 2011 |title=CS4803DGC Design and Programming of Game Console |url=https://faculty.cc.gatech.edu/~hyesoon/spr11/lec_cell.pdf}}</ref><ref>{{Cite book |last=Koranne |first=Sandeep |url=https://books.google.com/books?id=f9FxS-mdF8UC&pg=PA19 |title=Practical Computing on the Cell Broadband Engine |date=2009 |publisher=Springer Science+Business Media |isbn=9781441903082 |page=19}}</ref><ref>{{Cite web |last=Hofstee |first=H. Peter |date=2005 |title=All About the Cell Processor |url=http://www.research.ibm.com/people/a/ashwini/E3%202005%20Cell%20Blade%20reports/All_About_Cell_Cool_Chips_Final.pdf |url-status=dead |archive-url=https://web.archive.org/web/20110906154333/http://www.research.ibm.com/people/a/ashwini/E3%202005%20Cell%20Blade%20reports/All_About_Cell_Cool_Chips_Final.pdf |archive-date=September 6, 2011}}</ref> is the [[PowerPC]] based, dual-issue in-order two-way [[Simultaneous multithreading|simultaneous-multithreaded]] [[CPU]] core with a 23-stage pipeline acting as the controller for the eight SPEs, which handle most of the computational workload. PPE has limited out of order execution capabilities; it can perform loads out of order and has delayed execution pipelines. The PPE will work with conventional operating systems due to its similarity to other 64-bit PowerPC processors, while the SPEs are designed for vectorized floating point code execution. The PPE contains a 32 [[KiB]] level 1 instruction [[CPU cache|cache]], a 32 KiB level 1 data cache, and a 512 KiB level 2 cache. The size of a cache line is 128 bytes in all caches.<ref name="cbe-programming-handbok" />{{rp|pages=136–137,141}} Additionally, IBM has included an [[AltiVec]] (VMX) unit<ref name="seminar">{{Cite news |date=February 16, 2005 |title=Power Efficient Processor Design and the Cell Processor |url=http://www.cerc.utexas.edu/vlsi-seminar/spring05/slides/2005.02.16.hph.pdf |url-status=dead |archive-url=https://web.archive.org/web/20050426183838/http://www.cerc.utexas.edu/vlsi-seminar/spring05/slides/2005.02.16.hph.pdf |archive-date=April 26, 2005 |access-date=June 12, 2005 |publisher=IBM}}</ref> which is fully pipelined for [[single precision]] floating point (Altivec 1 does not support [[double precision]] floating-point vectors.), 32-bit [[Arithmetic logic unit|Fixed Point Unit (FXU)]] with 64-bit register file per thread, [[Load–store unit|Load and Store Unit (LSU)]], 64-bit [[Floating-point unit|Floating-Point Unit (FPU)]], [[Branch predictor|Branch Unit (BRU)]] and Branch Execution Unit(BXU).<ref name="cc.gatech.edu" />
PPE consists of three main units: Instruction Unit (IU), Execution Unit (XU), and vector/scalar execution unit (VSU). IU contains L1 instruction cache, branch prediction hardware, instruction buffers, and dependency checking logic. XU contains integer execution units (FXU) and load-store unit (LSU). VSU contains all of the execution resources for FPU and VMX. Each PPE can complete two double-precision operations per clock cycle using a scalar fused-multiply-add instruction, which translates to 6.4&nbsp;[[GFLOPS]] at 3.2&nbsp;GHz; or eight single-precision operations per clock cycle with a vector fused-multiply-add instruction, which translates to 25.6&nbsp;GFLOPS at 3.2&nbsp;GHz.<ref name="pacellperf">{{Cite web |last=Chen |first=Thomas |last2=Raghavan |first2=Ram |last3=Dale |first3=Jason |last4=Iwata |first4=Eiji |date=November 29, 2005 |title=Cell Broadband Engine Architecture and its first implementation |url=http://www.ibm.com/developerworks/power/library/pa-cellperf/ |url-status=dead |archive-url=https://web.archive.org/web/20121027092540/http://www.ibm.com/developerworks/power/library/pa-cellperf/ |archive-date=October 27, 2012 |access-date=September 9, 2012 |website=IBM developerWorks}}</ref><!-- use of KiB is intentional, please do not modify -->

====Xenon in Xbox 360====
The PPE was designed specifically for the Cell processor but during development, [[Microsoft]] approached IBM wanting a high-performance processor core for its [[Xbox 360]]. IBM complied and made the tri-core [[Xenon (processor)|Xenon processor]], based on a slightly modified version of the PPE with added VMX128 extensions.<ref>{{Cite web |last=Alexander |first=Leigh |date=January 16, 2009 |title=Processing The Truth: An Interview With David Shippy] |url=https://www.gamedeveloper.com/business/processing-the-truth-an-interview-with-david-shippy |website=[[Gamasutra]]}}</ref><ref>{{Cite news |last=Last |first=Jonathan V. |date=December 30, 2008 |title=Playing the Fool |url=https://www.wsj.com/articles/SB123069467545545011 |work=[[Wall Street Journal]]}}</ref>