Editing Central processing unit (section)

==Operation==
The fundamental operation of most CPUs, regardless of the physical form they take, is to execute a sequence of stored [[instruction (computing)|instructions]] that is called a program. The instructions to be executed are kept in some kind of [[Memory (computers)|computer memory]]. Nearly all CPUs follow the fetch, decode and execute steps in their operation, which are collectively known as the [[instruction cycle]].

After the execution of an instruction, the entire process repeats, with the next instruction cycle normally fetching the next-in-sequence instruction because of the incremented value in the [[program counter]]. If a jump instruction was executed, the program counter will be modified to contain the address of the instruction that was jumped to and program execution continues normally. In more complex CPUs, multiple instructions can be fetched, decoded and executed simultaneously. This section describes what is generally referred to as the "[[classic RISC pipeline]]", which is quite common among the simple CPUs used in many electronic devices (often called microcontrollers). It largely ignores the important role of CPU cache, and therefore the access stage of the pipeline.

Some instructions manipulate the program counter rather than producing result data directly; such instructions are generally called "jumps" and facilitate program behavior like [[Control flow#Loops|loops]], conditional program execution (through the use of a conditional jump), and existence of [[Subroutine|functions]].{{Efn|Some early computers, like the Harvard Mark I, did not support any kind of "jump" instruction, effectively limiting the complexity of the programs they could run. It is largely for this reason that these computers are often not considered to contain a proper CPU, despite their close similarity to stored-program computers.}} In some processors, some other instructions change the state of bits in a [[Status register|"flags" register]]. These flags can be used to influence how a program behaves, since they often indicate the outcome of various operations. For example, in such processors a "compare" instruction evaluates two values and sets or clears bits in the flags register to indicate which one is greater or whether they are equal; one of these flags could then be used by a later jump instruction to determine program flow.

===Fetch===
Fetch involves retrieving an [[instruction (computing)|instruction]] (which is represented by a number or sequence of numbers) from program memory. The instruction's location (address) in program memory is determined by the [[program counter]] (PC; called the "instruction pointer" in [[x86|Intel x86 microprocessors]]), which stores a number that identifies the address of the next instruction to be fetched. After an instruction is fetched, the PC is incremented by the length of the instruction so that it will contain the address of the next instruction in the sequence.{{Efn|Since the program counter counts ''memory addresses'' and not ''instructions'', it is incremented by the number of memory units that the instruction word contains. In the case of simple fixed-length instruction word ISAs, this is always the same number. For example, a fixed-length 32-bit instruction word ISA that uses 8-bit memory words would always increment the PC by four (except in the case of jumps). ISAs that use variable-length instruction words increment the PC by the number of memory words corresponding to the last instruction's length.}} Often, the instruction to be fetched must be retrieved from relatively slow memory, causing the CPU to stall while waiting for the instruction to be returned. This issue is largely addressed in modern processors by caches and pipeline architectures (see below).

===Decode===
{{Further|Instruction set architecture#Instruction encoding}}

The instruction that the CPU fetches from memory determines what the CPU will do. In the decode step, performed by [[binary decoder]] circuitry known as the ''instruction decoder'', the instruction is converted into signals that control other parts of the CPU.

The way in which the instruction is interpreted is defined by the CPU's instruction set architecture (ISA).{{Efn|Because the instruction set architecture of a CPU is fundamental to its interface and usage, it is often used as a classification of the "type" of CPU. For example, a "PowerPC CPU" uses some variant of the PowerPC ISA. A CPU of a certain ISA can execute a different ISA by running an emulator.}} Often, one group of bits (that is, a "field") within the instruction, called the [[opcode]], indicates which operation is to be performed, while the remaining fields usually provide supplemental information required for the operation, such as the operands. Those operands may be specified as a constant value (called an immediate value), or as the location of a value that may be a [[processor register]] or a memory address, as determined by some [[addressing mode]].

In some CPU designs, the instruction decoder is implemented as a hardwired, unchangeable binary decoder circuit. In others, a [[microprogram]] is used to translate instructions into sets of CPU configuration signals that are applied sequentially over multiple clock pulses. In some cases the memory that stores the microprogram is rewritable, making it possible to change the way in which the CPU decodes instructions.

===Execute===
After the fetch and decode steps, the execute step is performed. Depending on the CPU architecture, this may consist of a single action or a sequence of actions. During each action, control signals electrically enable or disable various parts of the CPU so they can perform all or part of the desired operation. The action is then completed, typically in response to a clock pulse. Very often the results are written to an internal CPU register for quick access by subsequent instructions. In other cases results may be written to slower, but less expensive and higher capacity [[random-access memory|main memory]].

For example, if an instruction that performs addition is to be executed, registers containing operands (numbers to be summed) are activated, as are the parts of the [[arithmetic logic unit]] (ALU) that perform addition. When the clock pulse occurs, the operands flow from the source registers into the ALU, and the sum appears at its output. On subsequent clock pulses, other components are enabled (and disabled) to move the output (the sum of the operation) to storage (e.g., a register or memory). If the resulting sum is too large (i.e., it is larger than the ALU's output word size), an arithmetic overflow flag will be set, influencing the next operation.