Editing Coprocessor (section)

==Other coprocessors==
* The [[MIPS architecture]] supports up to four coprocessor units, used for memory management, floating-point arithmetic, and two undefined coprocessors for other tasks such as graphics accelerators.<ref>Erin Farquhar, Philip Bunce, ''The MIPS programmer's handbook'', Morgan Kaufmann, 1994 {{ISBN|1-55860-297-6}}, appendix A3 page 330</ref>
* Using [[field-programmable gate array|FPGA]] (field-programmable gate arrays), custom coprocessors can be created for acceleration of particular processing tasks such as digital signal processing (e.g. [[Zynq]], combines [[ARM architecture|ARM]] cores with FPGA on a single die).
* [[TLS acceleration|TLS/SSL accelerator]]s, used on [[Server (computing)|server]]s; such accelerators used to be cards, but in modern times are instructions for crypto in mainstream CPUs.
* Some [[multi-core (computing)|multi-core]] chips can be programmed so that one of their processors is the primary processor, and the other processors are supporting coprocessors.
* China's [[Matrix 2000]] 128 core PCI-e coprocessor is a proprietary accelerator that requires a CPU to run it, and has been employed in an upgrade of the 17,792 node [[Tianhe-2]] supercomputer (2 Intel Knights Bridge+ 2 Matrix 2000 each), now dubbed 2A, roughly doubling its speed at 95 petaflops, exceeding the [[Sunway TaihuLight|world's fastest supercomputer]].<ref>{{cite web|url=https://www.hpcwire.com/2017/09/25/chinas-tianhe-2a-will-use-proprietary-accelerator-boast-94-petaflops-peak/|title=China's Tianhe-2A will Use Proprietary Accelerator and Boast 95 Petaflops Peak|date=25 September 2017|website=hpcwire.com|access-date=7 April 2018|archive-date=1 December 2020|archive-url=https://web.archive.org/web/20201201021841/https://www.hpcwire.com/2017/09/25/chinas-tianhe-2a-will-use-proprietary-accelerator-boast-94-petaflops-peak/|url-status=live}}</ref>
* A range of coprocessors were available for various models from [[Acorn Computers]], notably the [[BBC Micro]] and [[BBC Master]] series. Rather than special-purpose graphics or arithmetic devices, these were general-purpose CPUs (principally the 6502, Zilog Z80, National Semiconductor 32016, and ARM 1) described as second processors, typically interfaced to the host system using a message passing architecture known as the [[Tube (BBC Micro)|Tube]], with Acorn's own products providing such processors in a [[BBC Micro expansion unit]] with accompanying memory and interfacing circuitry. Software could be executed independently on the second processor, and applications could be written to offload work from the host system, leaving it to perform input/output tasks, resulting in acceleration. Since a range of CPUs were available in a variety of products, a BBC Micro fitted with such a coprocessor was able to run operating systems for other processor architectures, such as CP/M, DOS and Unix, along with accompanying software.