Editing Cray-3 (section)

===CPU design===
[[File:Cray-3 complete module.jpg|right|288px|thumb|Typical module layout, with a 4x4 arrangement of "submodules", stacked 4-deep. The metal connectors on the bottom are power connections.]]

As with previous designs, the core of the Cray-3 consisted of a number of [[Computer module|modules]], each containing several circuit boards packed with parts. In order to increase density, the individual [[GaAs]] chips were not [[Integrated circuit packaging|packaged]], and instead several were mounted directly with ultrasonic gold bonding to a board approximately {{convert|1|inch}} square. The boards were then turned over and mated to a second board carrying the electrical wiring, with wires on this card running through holes to the "bottom" (opposite the chips) side of the chip carrier where they were bonded, hence sandwiching the chip between the two layers of board.  These ''submodules'' were then stacked four-deep and, as in the Cray-2, wired to each other to make a 3D circuit.{{sfn|Lester|1993}}

Unlike the Cray-2, the Cray-3 modules also included [[edge connector]]s. Sixteen such submodules were connected together in a 4×4 array to make a single module measuring {{convert|121 × 107 × 7|mm|in}}. Even with this advanced packaging the circuit density was low even by 1990s standards, at about 96,000 gates per cubic inch.{{sfn|Brochure|1993|p=8}} Modern CPUs offer gate counts of millions per square inch, and the move to 3D circuits was still just being considered {{asof|2017|lc=yes}}.<ref>{{cite magazine |first=Jared |last=Newman |url=http://www.pcworld.com/article/227260/intels_3d_transistor_why_it_matters.html |title=Intel's 3D Transistor: Why It Matters |magazine=PCWorld |date=5 May 2011}}</ref>

Thirty-two such modules were then stacked and wired together with a mass of twisted-pair wires into a single processor. The basic cycle time was 2.11&nbsp;ns, or 474&nbsp;MHz, allowing each processor to reach about 0.948 [[GFLOPS]], and a 16 processor machine a theoretical 15.17 GFLOP. Key to the high performance was the high-speed access to main memory, which allowed each process to burst up to 8 GB/s.<ref>{{cite web |first=Aad |last=van der Steen |url=http://netlib2.cs.utk.edu/benchmark/top500/reports/report94/Architec/node6.html |title=Short Description of Architectures in the TOP500: The Cray Computer Corporation Cray-3 |website= TOP500 |date=14 November 1995 |archive-url=https://web.archive.org/web/20120328110827/http://netlib2.cs.utk.edu/benchmark/top500/reports/report94/Architec/node6.html |archive-date=28 March 2012}}</ref>