Editing DEC Alpha (section)

==Design principles==
The Alpha architecture was intended to be a high-performance design. Digital intended the architecture to support a one-thousandfold increase in performance over twenty-five years. To ensure this, any architectural feature that impeded multiple instruction issue, clock rate or multiprocessing was removed. As a result, the Alpha does not have:

* [[Branch delay slot]]s
* Suppressed instructions{{Clarify|date=January 2023|reason=Is this referring to instructions in a conditionalbranch delay slot not being executed if the branch is not taken?  This is often called nullification, not suppression.}}
* Byte load or store instructions (later added with the Byte Word Extensions (BWX))<ref>{{cite web
|title=The Alpha AXP, part 8: Memory access, storing bytes and words and unaligned data
|url=https://devblogs.microsoft.com/oldnewthing/20170816-00/?p=96825
|date=August 16, 2017
|quote=Dealing with unaligned memory on the Alpha AXP is very annoying
|access-date=July 18, 2022
}}</ref><ref>{{cite web
|quote=The instructions that comprise the BWX extension are ...
|title=Alpha 21264 Microprocessor Data Sheet
|url=https://www.star.bnl.gov/public/daq/HARDWARE/21264_data_sheet.pdf
|access-date=2018-09-20
|archive-date=2017-08-30
|archive-url=https://web.archive.org/web/20170830002919/http://www.star.bnl.gov/public/daq/HARDWARE/21264_data_sheet.pdf
|url-status=live
}}</ref>

===Condition codes===
The Alpha does not have [[Status register|condition code]]s for integer instructions<ref>{{cite web
|title=MIPS Instructions
|url=http://eas.uccs.edu/~cwang/ECE4480_sp_16/ch2(3rdEdition).PPT
|quote=DEC Alpha ... , no integer condition code.
}}{{Dead link|date=February 2022 |bot=InternetArchiveBot |fix-attempted=yes}}</ref> to remove a potential bottleneck at the condition status register. Instructions resulting in an overflow, such as adding two numbers whose result does not fit in 64 bits, write the 32 or 64 [[least significant bit]]s to the destination register. The carry is generated by performing an unsigned compare on the result with either operand to see if the result is smaller than either operand. If the test was true, the value one is written to the least significant bit of the destination register to indicate the condition.