Editing Direct memory access (section)

=== Cycle stealing mode ===
The ''[[cycle stealing]] mode'' is used in systems in which the CPU should not be disabled for the length of time needed for burst transfer modes. In the cycle stealing mode, the DMA controller obtains access to the system bus the same way as in burst mode, using ''BR ([[Bus Request]])'' and ''BG ([[Bus Grant]])'' signals, which are the two signals controlling the interface between the CPU and the DMA controller. However, in cycle stealing mode, after one unit of data transfer, the control of the system bus is deasserted to the CPU via BG. It is then continually requested again via BR, transferring one unit of data per request, until the entire block of data has been transferred.<ref>{{cite book |title=Computer Architecture and Organization |last=Hayes |first=John.P |isbn=0-07-027363-4 |year=1978 |page=426-427 |publisher=McGraw-Hill International Book Company }}</ref> By continually obtaining and releasing the control of the system bus, the DMA controller essentially interleaves instruction and data transfers. The CPU processes an instruction, then the DMA controller transfers one data value, and so on. Data is not transferred as quickly, but CPU is not idled for as long as in burst mode. Cycle stealing mode is useful for controllers that monitor data in real time.