Editing Emotion Engine (section)

=== Internal data bus ===
Communications between the MIPS core, the two VPUs, GIF, memory controller and other units is handled by a 128-bit wide internal data bus running at half the clock frequency of the Emotion Engine but, to offer greater bandwidth, there is also a 128-bit dedicated path between the CPU and VPU0 and a 128-bit dedicated path between VPU1 and GIF. At 150&nbsp;MHz, the internal data bus provides a maximum theoretical bandwidth of 2.4&nbsp;GB/s.