Editing Field-programmable gate array (section)

== Design ==
Contemporary FPGAs have ample [[logic gate]]s and RAM blocks to implement complex digital computations. FPGAs can be used to implement any logical function that an [[ASIC]] can perform. The ability to update the functionality after shipping, [[partial re-configuration]] of a portion of the design<ref>{{cite book| last1 = Wisniewski| first1 = Remigiusz| title = Synthesis of compositional microprogram control units for programmable devices| year = 2009| publisher = University of Zielona Góra| location = Zielona Góra| isbn = 978-83-7481-293-1| page = 153| url = http://zbc.uz.zgora.pl/Content/27955}}{{Dead link|date=February 2022 |bot=InternetArchiveBot |fix-attempted=yes }}</ref> and the low non-recurring engineering costs relative to an ASIC design (notwithstanding the generally higher unit cost), offer advantages for many applications.<ref name="FPGA">{{cite web|url=http://www.eecg.toronto.edu/~vaughn/challenge/fpga_arch.html|title=FPGA Architecture for the Challenge|work=toronto.edu|publisher=[[University of Toronto]]}}</ref>

As FPGA designs employ very fast I/O rates and bidirectional data [[Bus (computing)|buses]], it becomes a challenge to verify correct timing of valid data within setup time and hold time.<ref>{{cite book |last1=Oklobdzija |first1=Vojin G. |title=Digital Design and Fabrication |date=2017 |publisher=CRC Press |isbn=9780849386046 |url=https://books.google.com/books?id=VOnyWUUUj04C&dq=fpga+logic+gates+ram+blocks&pg=SA9-PA6}}</ref> [[Floorplan (microelectronics)|Floor planning]] helps resource allocation within FPGAs to meet these timing constraints.

Some FPGAs have analog features in addition to digital functions. The most common analog feature is a programmable [[slew rate]] on each output pin. This allows the user to set low rates on lightly loaded pins that would otherwise [[Electrical resonance|ring]] or [[Coupling (electronics)|couple]] unacceptably, and to set higher rates on heavily loaded high-speed channels that would otherwise run too slowly.<ref>{{cite web|url=http://wiki.altium.com/display/ADOH/FPGA+SI+Tutorial+-+Simulating+the+Reflection+Characteristics|title=FPGA Signal Integrity tutorial|work=altium.com|access-date=2010-06-15|archive-url=https://web.archive.org/web/20160307162907/http://wiki.altium.com/display/adoh/fpga+si+tutorial+-+simulating+the+reflection+characteristics|archive-date=2016-03-07|url-status=dead}}</ref><ref>[http://klabs.org/richcontent/fpga_content/DesignNotes/signal_quality/actel_drive_strength/index.htm NASA: FPGA drive strength] {{webarchive |url=https://web.archive.org/web/20101205230408/http://klabs.org/richcontent/fpga_content/DesignNotes/signal_quality/actel_drive_strength/index.htm |date=2010-12-05}}</ref> Also common are quartz-[[crystal oscillator]] driver circuitry, on-chip [[RC oscillator]]s, and [[phase-locked loop]]s with embedded [[voltage-controlled oscillator]]s used for clock generation and management as well as for high-speed serializer-deserializer (SERDES) transmit clocks and receiver clock recovery. Fairly common are differential [[comparator]]s on input pins designed to be connected to [[differential signaling]] channels. A few [[mixed signal]] FPGAs have integrated peripheral [[analog-to-digital converter]]s (ADCs) and [[digital-to-analog converter]]s (DACs) with analog signal conditioning blocks, allowing them to operate as a [[system on a chip]] (SoC).<ref>{{cite magazine |author=Mike Thompson |url=https://www.design-reuse.com/articles/16197/mixed-signal-fpgas-provide-green-power.html |title=Mixed-signal FPGAs provide GREEN POWER |magazine=Design & Reuse |date=2007-07-02}}</ref> Such devices blur the line between an FPGA, which carries digital ones and zeros on its internal programmable interconnect fabric, and [[field-programmable analog array]] (FPAA), which carries analog values on its internal programmable interconnect fabric.

=== Logic blocks ===
{{Main|Logic block}}
[[File:FPGA cell example.png|thumb|Simplified example illustration of a logic cell (LUT&nbsp;&ndash; [[lookup table]], FA&nbsp;&ndash; [[full adder]], DFF&nbsp;&ndash; [[D-type flip-flop]])]]

The most common FPGA architecture consists of an array of [[logic block]]s called configurable logic blocks (CLBs) or logic array blocks (LABs) (depending on vendor), [[I/O address|I/O pads]], and routing channels.<ref name="FPGA" /> Generally, all the routing channels have the same width (number of signals). Multiple I/O pads may fit into the height of one row or the width of one column in the array.

"An application circuit must be mapped into an FPGA with adequate resources. While the number of logic blocks and I/Os required is easily determined from the design, the number of routing channels needed may vary considerably even among designs with the same amount of logic. For example, a [[crossbar switch]] requires much more routing than a [[systolic array]] with the same gate count. Since unused routing channels increase the cost (and decrease the performance) of the FPGA without providing any benefit, FPGA manufacturers try to provide just enough channels so that most designs that will fit in terms of [[Lookup table#Hardware LUTs|lookup tables]] (LUTs) and I/Os can be [[Routing (electronic design automation)|routed]]. This is determined by estimates such as those derived from [[Rent's rule]] or by experiments with existing designs."<ref>{{Cite journal |last1=M.b |first1=Swami |last2=V.p |first2=Pawar |date=2014-07-31 |title=VLSI DESIGN: A NEW APPROACH |url=https://bioinfopublication.org/pages/article.php?id=BIA0002301 |journal=Journal of Intelligence Systems |language=En |volume=4 |issue=1 |pages=60–63 |issn=2229-7057}}</ref>

In general, a logic block consists of a few logical cells. A typical cell consists of a 4-input LUT, a [[Adder (electronics)|full adder]] (FA) and a [[D-type flip-flop]]. The LUT might be split into two 3-input LUTs. In ''normal mode'' those are combined into a 4-input LUT through the first [[multiplexer]] (mux). In ''arithmetic'' mode, their outputs are fed to the adder. The selection of mode is programmed into the second mux. The output can be either [[Synchronous circuit|synchronous]] or [[Asynchronous circuit|asynchronous]], depending on the programming of the third mux. In practice, the entire adder or parts of it are [[Shannon expansion|stored as functions]] into the LUTs in order to save [[Circuit utilization|space]].<ref>[http://www.altera.com/literature/hb/cyc2/cyc2_cii51002.pdf 2. CycloneII Architecture]. Altera. February 2007</ref><ref>{{cite web |url=http://www.altera.com/literature/hb/stratix-iv/stx4_5v1_01.pdf |title=Documentation: Stratix IV Devices |publisher=Altera.com |date=2008-06-11 |access-date=2013-05-01 |archive-url=https://web.archive.org/web/20110926214034/http://www.altera.com/literature/hb/stratix-iv/stx4_5v1_01.pdf |archive-date=2011-09-26 |url-status=dead}}</ref><ref>[http://www.xilinx.com/support/documentation/user_guides/ug070.pdf Virtex-4 FPGA User Guide] (December 1st, 2008). Xilinx, Inc.</ref>

=== Hard blocks ===
Modern FPGA families expand upon the above capabilities to include higher-level functionality fixed in silicon. Having these common functions embedded in the circuit reduces the area required and gives those functions increased performance compared to building them from logical primitives. Examples of these include [[Binary multiplier|multipliers]], generic [[Digital signal processor|DSP blocks]], [[Microprocessor|embedded processors]], high-speed I/O logic and embedded [[Computer memory|memories]].

Higher-end FPGAs can contain high-speed [[multi-gigabit transceiver]]s and ''hard IP cores'' such as [[processor core]]s, [[Ethernet]] [[Medium access control|medium access control units]], [[Conventional PCI|PCI]] or [[PCI Express]] controllers, and external [[memory controller]]s. These cores exist alongside the programmable fabric, but they are built out of [[transistor]]s instead of LUTs so they have ASIC-level performance and power consumption without consuming a significant amount of fabric resources, leaving more of the fabric free for the application-specific logic. The multi-gigabit transceivers also contain high-performance [[signal conditioning]] circuitry along with high-speed serializers and deserializers, components that cannot be built out of LUTs. Higher-level physical layer (PHY) functionality such as [[line coding]] may or may not be implemented alongside the serializers and deserializers in hard logic, depending on the FPGA.

=== Soft core ===
[[File:Xilinx Zynq-7000 AP SoC.jpg|thumb|A [[Xilinx]] Zynq-7000 all-programmable system on a chip]]

An alternate approach to using hard macro processors is to make use of [[soft processor]] [[Semiconductor intellectual property core|IP cores]] that are implemented within the FPGA logic. [[Nios II]], [[MicroBlaze]] and [[Mico32]] are examples of popular softcore processors. Many modern FPGAs are programmed at ''run time'', which has led to the idea of [[reconfigurable computing]] or reconfigurable systems&nbsp;– [[CPU]]s that reconfigure themselves to suit the task at hand. Additionally, new non-FPGA architectures are beginning to emerge. Software-configurable microprocessors such as the Stretch S5000 adopt a hybrid approach by providing an array of processor cores and FPGA-like programmable cores on the same chip.

=== Integration ===
In 2012 the coarse-grained architectural approach was taken a step further by combining the [[logic block]]s and interconnects of traditional FPGAs with embedded [[microprocessor]]s and related peripherals to form a complete [[System on a chip|system on a programmable chip]]. Examples of such hybrid technologies can be found in the [[Xilinx]] Zynq-7000 all [[Programmable SoC]],<ref name="Xilinx-Inc-Oct-2011-8-K">{{cite web|url=http://edgar.secdatabase.com/520/95012311090713/filing-main.htm |title=Xilinx Inc, Form 8-K, Current Report, Filing Date Oct 19, 2011 |publisher=secdatabase.com |access-date =May 6, 2018}}</ref> which includes a 1.0&nbsp;[[GHz]] dual-core [[ARM Cortex-A9]] MPCore processor [[Embedded system|embedded]] within the FPGA's logic fabric,<ref name="Xilinx-Inc-May-2011-10-K">{{cite web|url=http://edgar.secdatabase.com/1249/95012311055454/filing-main.htm |title=Xilinx Inc, Form 10-K, Annual Report, Filing Date May 31, 2011 |publisher=secdatabase.com |access-date =May 6, 2018}}</ref> or in the [[Altera]] Arria V FPGA, which includes an 800&nbsp;MHz [[dual-core]] [[ARM Cortex-A9]] MPCore. The [[Atmel]] FPSLIC is another such device, which uses an [[Atmel AVR|AVR]] processor in combination with Atmel's programmable logic architecture. The [[Microsemi]] [[SmartFusion]] devices incorporate an ARM Cortex-M3 hard processor core (with up to 512&nbsp;kB of [[Flash memory|flash]] and 64&nbsp;kB of RAM) and analog [[peripheral]]s such as a multi-channel [[analog-to-digital converter]]s and [[digital-to-analog converter]]s in their [[flash memory]]-based FPGA fabric.{{cn|date=November 2022}}

=== Clocking ===
Most of the logic inside of an FPGA is [[synchronous circuit]]ry that requires a [[clock signal]]. FPGAs contain dedicated global and regional routing networks for clock and reset, typically implemented as an [[H tree]], so they can be delivered with minimal [[Clock skew|skew]]. FPGAs may contain analog [[phase-locked loop]] or [[delay-locked loop]] components to synthesize new [[clock frequencies]] and manage [[jitter]]. Complex designs can use multiple clocks with different frequency and phase relationships, each forming separate [[clock domain]]s. These clock signals can be generated locally by an oscillator or they can be recovered from a [[data stream]]. Care must be taken when building [[clock domain crossing]] circuitry to avoid [[Metastability (electronics)|metastability]]. Some FPGAs contain [[dual port RAM]] blocks that are capable of working with different clocks, aiding in the construction of building [[FIFO (computing and electronics)|FIFOs]] and dual port buffers that bridge clock domains.

=== 3D architectures ===
To shrink the size and power consumption of FPGAs, vendors such as [[Tabula (company)|Tabula]] and [[Xilinx]] have introduced [[three-dimensional integrated circuit|3D or stacked architectures]].<ref>Dean Takahashi, VentureBeat. "[https://venturebeat.com/2011/05/02/intel-connection-helped-chip-startup-tabula-raise-108m Intel connection helped chip startup Tabula raise $108M]." May 2, 2011. Retrieved May 13, 2011.</ref><ref name="lawrence">Lawrence Latif, The Inquirer. "[https://web.archive.org/web/20101029124903/http://www.theinquirer.net/inquirer/news/1811460/fpga-manufacturer-claims-beat-moores-law FPGA manufacturer claims to beat Moore's Law]." October 27, 2010. Retrieved May 12, 2011.</ref> Following the introduction of its [[28 nm|28&nbsp;nm]] 7-series FPGAs, Xilinx said that several of the highest-density parts in those FPGA product lines will be constructed using multiple dies<!--dice or dies is correct for integrated circuits&nbsp;— Wiktionary--> in one package, employing technology developed for 3D construction and stacked-die assemblies.

Xilinx's approach stacks several (three or four) active FPGA dies side by side on a silicon [[interposer]]&nbsp;– a single piece of silicon that carries passive interconnect.<ref name="lawrence" /><ref>EDN Europe. "[http://www.edn-europe.com/xilinxadoptsstackeddie3dpackaging+article+4461+Europe.html Xilinx adopts stacked-die 3D packaging] {{Webarchive|url=https://web.archive.org/web/20110219182606/http://www.edn-europe.com/xilinxadoptsstackeddie3dpackaging+article+4461+Europe.html |date=2011-02-19 }}." November 1, 2010. Retrieved May 12, 2011.</ref> The multi-die construction also allows different parts of the FPGA to be created with different process technologies, as the process requirements are different between the FPGA fabric itself and the very high speed 28&nbsp;Gbit/s serial transceivers. An FPGA built in this way is called a ''[[Heterogeneous computing|heterogeneous]] FPGA''.<ref>{{Cite web|url=https://www.xilinx.com/support/documentation/white_papers/wp380_Stacked_Silicon_Interconnect_Technology.pdf |archive-url=https://web.archive.org/web/20101105113516/http://www.xilinx.com/support/documentation/white_papers/wp380_Stacked_Silicon_Interconnect_Technology.pdf |archive-date=2010-11-05 |url-status=live|title=Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity, Bandwidth, and Power Efficiency|last=Saban|first=Kirk|date=December 11, 2012|website=xilinx.com|access-date=2018-11-30}}</ref>

Altera's heterogeneous approach involves using a single monolithic FPGA die and connecting other dies and technologies to the FPGA using Intel's embedded multi_die interconnect bridge (EMIB) technology.<ref>{{cite web|url=http://www.intel.com/content/www/us/en/foundry/emib.html|title=Intel Custom Foundry EMIB|work=Intel|access-date=2015-07-13|archive-date=2015-07-13|archive-url=https://web.archive.org/web/20150713230215/http://www.intel.com/content/www/us/en/foundry/emib.html|url-status=dead}}</ref>