Editing Gate array (section)

== Design ==
{{Unsourced section|date=April 2023}}
A gate array is a prefabricated silicon chip with most [[transistor]]s having no predetermined function. These transistors can be connected by metal layers to form standard [[Negated AND gate|NAND]] or [[NOR gate|NOR]] [[logic gate]]s. These logic gates can then be further interconnected into a complete circuit on the same or later metal layers. The creation of a circuit with a specified function is accomplished by adding this final layer or layers of metal interconnects to the chip late in the manufacturing process, allowing the function of the chip to be customized as desired. These layers are analogous to the copper layers of a [[printed circuit board]].

The earliest gate arrays comprised [[bipolar transistors]], usually configured as high-performance [[transistor–transistor logic]], [[emitter-coupled logic]], or [[current-mode logic]] logic configurations. [[CMOS]] (complementary [[metal–oxide–semiconductor]]) gate arrays were later developed and came to dominate the industry.

Gate array master slices with unfinished chips arrayed across a [[wafer (electronics)|wafer]] are usually prefabricated and stockpiled in large quantities regardless of customer orders. The design and fabrication according to the individual customer specifications can be finished in a shorter time than [[standard cell]] or [[full custom]] design. The gate array approach reduces the non-recurring engineering [[Photomask|mask]] costs as fewer custom masks need to be produced. In addition, manufacturing test tooling lead time and costs are reduced — the same test fixtures can be used for all gate array products manufactured on the same [[Die (integrated circuit)|die]] size. Gate arrays were the predecessor of the more complex [[Structured ASIC platform|structured ASIC]]; unlike gate arrays, structured ASICs tend to include predefined or configurable memories and/or analog blocks.

An application circuit must be built on a gate array that has enough gates, wiring, and I/O pins. Since requirements vary, gate arrays usually come in families, with larger members having more of all resources, but correspondingly more expensive. While the designer can fairly easily count how many gates and I/Os pins are needed, the number of routing tracks needed may vary considerably even among designs with the same amount of logic. (For example, a [[crossbar switch]] requires much more routing than a [[systolic array]] with the same gate count.) Since unused routing tracks increase the cost (and decrease the performance) of the part without providing any benefit, gate array manufacturers try to provide just enough tracks so that most designs that will fit in terms of gates and I/O pins can be routed. This is determined by estimates such as those derived from [[Rent's rule]] or by experiments with existing designs.

The main drawbacks of gate arrays are their somewhat lower density and performance compared with other approaches to ASIC design. However, this style is often a viable approach for low production volumes.