Editing Harvard architecture (section)

==Modern uses of the Harvard architecture==
The principal advantage of the pure Harvard architecture—simultaneous access to more than one memory system—has been reduced by modified Harvard processors using modern [[CPU cache]] systems. Relatively pure Harvard architecture machines are used mostly in applications where trade-offs, like the cost and power savings from omitting caches, outweigh the programming penalties from featuring distinct code and data address spaces.

*[[Digital signal processors]] (DSPs) generally execute small, highly optimized audio or video processing algorithms using a Harvard architecture.<ref>{{cite journal |last1=Ungerboeck |first1=G. |last2=Maiwald |first2=D. |last3=Kaeser |first3=H. P. |last4=Chevillat |first4=P. R. |last5=Beraud |first5=J. P. |journal=IBM Journal of Research and Development |title=Architecture of a digital signal processor |date=1985 |volume=29 |number=2 |pages=132–139 |doi=10.1147/rd.292.0132 |url=https://ieeexplore.ieee.org/document/5390281|url-access=subscription }}</ref> They avoid caches because their behavior must be extremely reproducible. The difficulties of coping with multiple address spaces are of secondary concern to speed of execution. Consequently, some DSPs feature multiple data memories in distinct address spaces to facilitate [[Single instruction, multiple data|SIMD]] and [[VLIW]] processing. [[Texas Instruments TMS320]] C55x processors, for one example, feature multiple parallel data buses (two write, three read) and one instruction bus.
*[[Microcontrollers]] are characterized by having small amounts of program (flash memory) and data ([[Static random-access memory|SRAM]]) memory, and take advantage of the Harvard architecture to speed processing by concurrent instruction and data.<ref>{{cite conference  |last1=Hu |first1=Yue-li |last2=Cao |first2=Jia-lin |last3=Ran |first3=Feng |last4=Liang |first4=Zhi-jian |book-title=Proceedings of the Sixth IEEE CPMT Conference on High Density Microsystem Design and Packaging and Component Failure Analysis (HDP '04) |title=Design of a high performance microcontroller |date=2004 |pages=25–28 |doi=10.1109/HPD.2004.1346667 |isbn=0-7803-8620-5 |url=https://ieeexplore.ieee.org/document/1346667|url-access=subscription }}</ref> The separate storage means the program and data memories may feature different bit widths, for example using 16-bit-wide instructions and 8-bit-wide data. They also mean that [[instruction prefetch]] can be performed in parallel with other activities. Examples include the [[PIC microcontroller|PIC]] by [[Microchip Technology|Microchip Technology, Inc.]] and the [[Atmel AVR|AVR]] by [[Atmel|Atmel Corp]] (now part of Microchip Technology).

Even in these cases, it is common to employ special instructions in order to access program memory as though it were data for read-only tables, or for reprogramming; those processors are [[modified Harvard architecture]] processors.