Editing Hazard (computer architecture) (section)

===Generic===

==== {{Anchor|PIPELINE-FLUSH}}Pipeline bubbling ====
{{Main|Bubble (computing)}}

''Bubbling the pipeline'', also termed a ''pipeline break'' or ''pipeline stall'', is a method to preclude data, structural, and branch hazards. As instructions are fetched, control logic determines whether a hazard could/will occur. If this is true, then the control logic inserts {{Mono|no operation}}s ({{Mono|[[NOP (code)|NOP]]}}s) into the pipeline. Thus, before the next instruction (which would cause the hazard) executes, the prior one will have had sufficient time to finish and prevent the hazard. If the number of {{Mono|NOP}}s equals the number of stages in the pipeline, the processor has been cleared of all instructions and can proceed free from hazards. All forms of stalling introduce a delay before the processor can resume execution.

''Flushing the pipeline'' occurs when a branch instruction jumps to a new memory location, invalidating all prior stages in the pipeline.  These prior stages are cleared, allowing the pipeline to continue at the new instruction indicated by the branch.<ref>{{cite web
 | url = http://www.cs.iastate.edu/~prabhu/Tutorial/PIPELINE/branchPred.html
 | title = Branch Prediction Schemes
 | date = 2001-04-06 | access-date = 2014-07-19
 | website = cs.iastate.edu
}}</ref><ref>{{cite web
 | url = http://classes.soe.ucsc.edu/cmpe110/Winter04/pipelining.txt
 | title = Data and Control Hazards
 | date = 2004-02-23 | access-date = 2014-07-19
 | website = classes.soe.ucsc.edu
}}</ref>