Editing Host controller interface (USB, Firewire) (section)

===Enhanced Host Controller Interface{{Anchor|EHCI}}===
The '''Enhanced Host Controller Interface''' ('''EHCI''')<ref name="EHCI">{{cite web|url= http://www.intel.com/content/www/us/en/io/universal-serial-bus/ehci-specification.html |title= Enhanced Host Controller Interface Specification |website= Intel.com |date= |accessdate= 2017-01-10}}</ref> is a high-speed controller standard applicable to USB 2.0. UHCI- and OHCI-based systems, as existed previously, entailed greater complexity and [[cost]]s than necessary. Consequently, the [[USB Implementers Forum]] (USB-IF) insisted{{when|date=February 2017}} on a public specification for EHCI. Intel hosted EHCI [[conformance testing|conformance-testing]] and this helped to prevent the incursion of proprietary features.

Originally a PC providing high-speed ports had two controllers, one handling low- and full-speed devices and the second handling high-speed devices. Typically such a system had EHCI and either OHCI or UHCI drivers. The UHCI driver provides low- and full-speed interfaces for Intel or VIA chipsets' USB host controllers on the motherboard, or for any VIA discrete host controllers attached to the computer's expansion bus. The OHCI driver provides low- and full-speed functions for USB ports of all other motherboard chipset vendors' integrated USB host controllers or discrete host controllers attached to the computer's expansion bus. The EHCI driver provided high-speed functions for USB ports on the motherboard or on the discrete USB controller. More recent hardware routes all ports through an internal "rate-matching" hub (RMH) that converts all traffic involving any directly-connected ports working at full-speed and low-speed between the high-speed traffic presented to the EHCI controller and the full-speed or low-speed traffic that the ports operating at those speeds expect, allowing the EHCI controller to handle these devices.

The EHCI software interface specification defines both 32-bit and 64-bit versions of its data structures,<ref name="EHCI"/> so it does not need a bounce buffer or [[IOMMU]] to work with a 64-bit operating system if a rate-matching hub is implemented to provide full-speed and low-speed connectivity instead of companion controllers using either the UHCI specification or OHCI specification, both of which are 32-bit only specifications.