Editing Logical effort (section)

===Delay in an inverter===

[[Image:CMOS Inverter.svg|right|thumb|A CMOS inverter circuit.]]

By definition, the logical effort ''g'' of an inverter is 1.  If the inverter drives an equivalent inverter, the electrical effort ''h'' is also 1.

The parasitic delay ''p'' of an inverter is also 1 (this can be found by considering the [[Elmore delay]] model of the inverter).

Therefore, the total normalised delay of an inverter driving an equivalent inverter is

:<math>d = gh + p = (1)(1) + 1 = 2</math>