Editing MESI protocol (section)

==== Invalidate Queues ====

With regard to invalidation messages, CPUs implement invalidate queues, whereby incoming invalidate requests are instantly acknowledged but not immediately acted upon. Instead, invalidation messages simply enter an invalidation queue and their processing occurs as soon as possible (but not necessarily instantly).  Consequently, a CPU can be oblivious to the fact that a cache line in its cache is actually invalid, as the invalidation queue contains invalidations that have been received but haven't yet been applied.  Note that, unlike the store buffer, the CPU can't scan the invalidation queue, as that CPU and the invalidation queue are physically located on opposite sides of the cache.

As a result, memory barriers are required.  A ''store barrier'' will flush the store buffer, ensuring all writes have been applied to that CPU's cache.  A ''read barrier'' will flush the invalidation queue, thus ensuring that all writes by other CPUs become visible to the flushing CPU. Furthermore, memory management units do not scan the store buffer, causing similar problems. This effect is visible even in single threaded processors.<ref>{{Cite book | doi = 10.1007/978-3-319-12154-3_8| chapter = Store Buffer Reduction with MMUs| title = Verified Software: Theories, Tools and Experiments| volume = 8471| pages = 117| series = Lecture Notes in Computer Science| year = 2014| last1 = Chen | first1 = G. | last2 = Cohen | first2 = E. | last3 = Kovalev | first3 = M. | isbn = 978-3-319-12153-6}}</ref>