Editing MIPS Technologies (section)

=== MIPS eVocore RISC-V CPU IP cores ===
The MIPS eVocore CPUs are the first RISC-V CPU IP cores from MIPS. Both cores provide support for privileged hardware virtualization, user defined custom extensions, multi-threading, hybrid debug, and functional safety.<ref name=":0" /> They include:

* '''eVocore P8700:''' multiprocessing system combining a deep pipeline with multi-issue out-of-order (OOO) execution and multi-threading. It can scale up to 64 clusters, 512 cores and 1,024 harts/threads.<ref name=":0" />
* '''eVocore I8500:''' in-order multiprocessing system. Each core combines multi-threading and a triple-issue pipeline.<ref name=":0" />