Editing MMX (instruction set) (section)

== MMX in embedded applications ==
Intel's and [[Marvell Technology Group]]'s [[XScale]] microprocessor core starting with PXA270 include an [[SIMD]] [[instruction set architecture]] extension to the [[ARM architecture]] core named ''Intel Wireless MMX Technology'' (iwMMXt) which functions are similar to those of the [[IA-32]] MMX extension.<ref>{{cite web | url=https://www.intel.com/pressroom/archive/releases/2002/20020910net.htm | title= 	Intel Brings MMX™ Technology To Intel® Personal Internet Client Architecture-Based Wireless Devices  | access-date=28 July 2022}}</ref><ref>{{cite web | url=https://www.intel.com/pressroom/archive/releases/2004/20040412net.htm | title=Intel Delivers Next-Generation Processors Specifically Designed For Cell Phones And Wireless PDAs | access-date=28 July 2022 | url-status=live | archive-url=https://web.archive.org/web/20120102010704/https://www.intel.com/pressroom/archive/releases/2004/20040412net.htm | archive-date=2 January 2012 }}</ref><ref>{{cite web | url=https://www.eetimes.com/worlds-smallest-pxa270-embedded-cpu-card/ | title=World's smallest PXA270 embedded CPU card? | date=15 September 2004 | access-date=28 July 2022 | website=[[EE Times]]}}</ref> It provides arithmetic and logic operations on 64-bit integer numbers, in which the software may choose to instead perform two 32-bit, four 16-bit or eight 8-bit operations in one instruction. The extension contains 16 data registers of 64-bits and eight control registers of 32-bits. All registers are accessed through standard ARM architecture coprocessor mapping mechanism. iwMMXt occupies coprocessors 0 and 1 space, and some of its opcodes clash with the opcodes of the earlier floating-point extension, FPA.{{Citation needed|date=July 2022}}

Later versions of Marvell's ARM processors support both ''Wireless MMX'' (WMMX) and ''Wireless MMX2'' (WMMX2) opcodes.