Editing MOSFET (section)

=== Structure and channel formation ===
{{See also|Field effect (semiconductor)}}
[[file:Semiconductor band-bending-en.svg|thumb|upright=1.5|''Channel formation in nMOS MOSFET shown as [[band diagram]]'': Top panels: An applied gate voltage bends bands, depleting holes from surface (left). The charge inducing the bending is balanced by a layer of negative acceptor-ion charge (right). Bottom panel: A larger applied voltage further depletes holes but conduction band lowers enough in energy to populate a conducting channel.]]
[[file:Illustration of C-V measurement.gif|thumb|upright=1.5|C–V profile for a bulk MOSFET with different oxide thickness. The leftmost part of the curve corresponds to accumulation. The valley in the middle corresponds to depletion. The curve on the right corresponds to inversion.]]

A MOSFET is based on the modulation of charge concentration by a MOS capacitance between a ''body'' electrode and a ''gate'' electrode located above the body and insulated from all other device regions by a gate dielectric layer. If dielectrics other than an oxide are employed, the device may be referred to as a metal-insulator-semiconductor FET (MISFET). Compared to the MOS capacitor, the MOSFET includes two additional terminals (''source'' and ''drain''), each connected to individual highly doped regions that are separated by the body region. These regions can be either p or n type, but they must both be of the same type, and of opposite type to the body region. The source and drain (unlike the body) are highly doped as signified by a "+" sign after the type of doping.

If the MOSFET is an n-channel or nMOS FET, then the source and drain are ''n+'' regions and the body is a ''p'' region. If the MOSFET is a p-channel or pMOS FET, then the source and drain are ''p+'' regions and the body is a ''n'' region. The source is so named because it is the source of the charge carriers (electrons for n-channel, holes for p-channel) that flow through the channel; similarly, the drain is where the charge carriers leave the channel.

The occupancy of the energy bands in a semiconductor is set by the position of the [[Fermi level]] relative to the semiconductor energy-band edges.

{{See also|Depletion region}}
With sufficient gate voltage, the valence band edge is driven far from the Fermi level, and holes from the body are driven away from the gate.

At larger gate bias still, near the semiconductor surface the conduction band edge is brought close to the Fermi level, populating the surface with electrons in an ''inversion layer'' or ''n-channel'' at the interface between the p region and the oxide. This conducting channel extends between the source and the drain, and current is conducted through it when a voltage is applied between the two electrodes. Increasing the voltage on the gate leads to a higher electron density in the inversion layer and therefore increases the current flow between the source and drain. For gate voltages below the threshold value, the channel is lightly populated, and only a very small [[subthreshold leakage]] current can flow between the source and the drain.

When a negative gate-source voltage (positive source-gate) is applied, it creates a ''p-channel'' at the surface of the n region, analogous to the n-channel case, but with opposite polarities of charges and voltages. When a voltage less negative than the threshold value (a negative voltage for the p-channel) is applied between gate and source, the channel disappears and only a very small subthreshold current can flow between the source and the drain. The device may comprise a [[silicon on insulator]] device in which a buried oxide is formed below a thin semiconductor layer. If the channel region between the gate dielectric and the buried oxide region is very thin, the channel is referred to as an ultrathin channel region with the source and drain regions formed on either side in or above the thin semiconductor layer. Other semiconductor materials may be employed. When the source and drain regions are formed above the channel in whole or in part, they are referred to as raised source/drain regions.

{| class="wikitable"
|+ Comparison of n- and p-type MOSFETs<ref name=memory>{{cite web|title=memory components data book|url=http://bitsavers.trailing-edge.com/pdf/intel/_dataBooks/1984_Intel_Memory_Components_Handbook.pdf|archive-url=https://web.archive.org/web/20160304090142/http://bitsavers.trailing-edge.com/pdf/intel/_dataBooks/1984_Intel_Memory_Components_Handbook.pdf|url-status=dead|archive-date=4 March 2016|website=memory components data book|publisher=Intel|accessdate=30 August 2015|pages=2–1}}</ref>
|-
! colspan=2 | Parameter
! nMOSFET
! pMOSFET
|-
! colspan=2 | Source/drain type
| n-type
| p-type
|-
! colspan=2 | {{ubl|Channel type|(MOS capacitor)}}
| n-type
| p-type
|-
! rowspan=2 | {{ubl|Gate|type}}
! Polysilicon
| n+
| p+
|-
! Metal
| {{abbr|φ<sub>m</sub>|Metal's workfunction}} ~ Si conduction band
| φ<sub>m</sub> ~ Si valence band
|-
! colspan=2 | Well type
| p-type
| n-type
|-
! colspan=2 | Threshold voltage, ''V''{{sub|th}}
| {{ubl
 | Positive (enhancement)
 | Negative (depletion)
 }}
| {{ubl
 | Negative (enhancement)
 | Positive (depletion)
 }}
|-
! colspan=2 | Band-bending
| Downwards
| Upwards
|-
! colspan=2 | Inversion layer carriers
| Electrons
| Holes
|-
! colspan=2 | Substrate type
| p-type
| n-type
|}