Editing MOS Technology 6502 (section)

===Design notes===
Chuck Peddle, Rod Orgill, and Wil Mathys designed the initial architecture of the new processors. A September 1975 article in ''[[EDN (magazine)|EDN]]'' magazine gives this summary of the design:{{sfn|Cushman|1975|p=36}}
<blockquote>
The MOS Technology 650X family represents a conscious attempt of eight former Motorola employees who worked on the development of the 6800 system to put out a part that would replace and outperform the 6800, yet undersell it. With the benefit of hindsight gained on the 6800 project, the MOS Technology team headed by Chuck Peddle, made the following architectural changes in the Motorola CPU…
</blockquote>

The main change in terms of chip size was the elimination of the [[tri-state driver]]s from the address bus outputs. A three-state bus has states for ''1'', ''0'' and ''high impedance''. The last state is used to allow other devices to access the bus, and is typically used for [[multiprocessing]], or more commonly in these roles, for [[direct memory access]] (DMA). While useful, this feature is expensive in terms of on-chip circuitry. The 6502 simply removed this feature, in keeping with its design as an inexpensive controller being used for specific tasks and communicating with simple devices. Peddle suggested that anyone who required this style of access could implement it with a [[Multiplexer#List of ICs which provide multiplexing|74158]].{{sfn|Cushman|1975|p=41}}{{efn|One example of such a design was the [[Atari 8-bit computers]], which use DMA to share memory between the 6502 and the ANTIC video chip. This was implemented with a single flip-flop, which was later built into custom ''Sally'' versions of the 6502 used in these machines. The flip flop enabled a pair of 74LS244 bus drivers that could isolate the 6502's address bus when DMA was required.<ref>{{cite book |title=Games vs. Hardware. The History of PC video games: The 80's |first=John |last=Purcaru |date=2014 |page=317}}</ref>}}

The next major difference was to simplify the registers. To start with, one of the two [[Accumulator (computing)|accumulators]] was removed. General-purpose registers like accumulators have to be accessed by many parts of the instruction decoder, and thus require significant amounts of wiring to move data to and from their storage. Two accumulators makes many coding tasks easier but costs the chip design itself significant complexity.{{sfn|Cushman|1975|p=36}} Further savings were made by reducing the [[stack register]] from 16 to 8 bits, meaning that the stack could only be 256 bytes long, which was enough for its intended role as a microcontroller.{{sfn|Cushman|1975|p=36}}{{failed verification|date=January 2023}}

The 16-bit IX [[index register]] was split in two, becoming X and Y. More importantly, the style of access changed. In the 6800, IX held a 16-bit address which was offset by an 8-bit number stored with the instruction and added to the address. In the 6502 (and most other contemporary designs), the 16-bit base address was stored in the instruction, and the 8-bit X or Y was added to it.{{sfn|Cushman|1975|p=41}}

Finally, the instruction set was simplified, simplifying the decoder and control logic. Of the original 72 instructions in the 6800, 56 were implemented. Among those removed were instructions that operated between the 6800's two accumulators, and several branch instructions inspired by the [[PDP-11]].{{sfn|Cushman|1975|p=41}}

The chip's high-level design had to be turned into drawings of transistors and interconnects. At MOS Technology, the layout was a very manual process done with colored pencils and [[vellum paper]]. The layout consisted of thousands of polygon shapes on six different drawings; one for each layer of the fabrication process. Given the size limits, the entire chip design had to be constantly considered. Mensch and Paivinen worked on the [[instruction decoder]]{{sfn|Interview|2014|loc=1:01:00}} while Mensch, Peddle and Orgill worked on the ALU and registers. A further advance, developed at a party, was a way to share some of the internal wiring to allow the ALU to be reduced in size.{{sfn|Interview|2014|loc=1:02:00}}

Despite their best efforts, the final design ended up being larger than the original target. The first 6502 chips were {{convert|168|×|183|mil}}, for an area of {{val|19.8|u=mm2}}. The original version of the processor had no rotate right (ROR) capability, so the instruction was omitted from the original documentation. The next iteration of the design shrank the chip and added the rotate right capability, and ROR was included in revised documentation.<ref name="ROR">[[:File:MCS650x Instruction Set.jpg]]</ref>{{efn|Since the OP code still did something in the original version of the processor, just not a correct ROR instruction, this caused a persistent myth that the original 6502 had a bug in its ROR instruction.<ref>{{Cite web|url=https://www.pagetable.com/?p=406|title=Measuring the ROR Bug in the Early MOS 6502 – pagetable.com|access-date=2023-02-25|archive-date=2023-03-21|archive-url=https://web.archive.org/web/20230321144032/https://www.pagetable.com/?p=406|url-status=live}}</ref><ref>{{cite web | url=https://www.applefritter.com/content/how-test-ceramic-6502-ror-bug | title=How to test a ceramic 6502 for the ROR bug? &#124; Applefritter | access-date=2023-02-25 | archive-date=2023-02-25 | archive-url=https://web.archive.org/web/20230225154458/https://www.applefritter.com/content/how-test-ceramic-6502-ror-bug | url-status=live }}</ref><ref>{{cite web | url=https://www.youtube.com/watch?v=Uk_QC1eU0Fg | title=The 6502 Rotate Right Myth | website=[[YouTube]] | access-date=2023-02-25 | archive-date=2023-02-25 | archive-url=https://web.archive.org/web/20230225154447/https://www.youtube.com/watch?v=Uk_QC1eU0Fg | url-status=live }}</ref>}}