Editing Magnetoresistive RAM (section)

===Speed===
[[Dynamic random-access memory]] (DRAM) performance is limited by the rate at which the charge stored in the cells can be drained (for reading) or stored (for writing). MRAM operation is based on measuring voltages rather than charges or currents, so there is less "settling time" needed. IBM researchers have demonstrated MRAM devices with access times on the order of 2&nbsp;ns, somewhat better than even the most advanced DRAMs built on much newer processes.<ref>[http://www.thic.org/pdf/Jul03/nist.skaka.030722.pdf "Past, Present and Future of MRAM"], NIST Magnetic Technology, 22 July 2003</ref> A team at the German [[Physikalisch-Technische Bundesanstalt]] have demonstrated MRAM devices with 1&nbsp;ns settling times, better than the currently accepted theoretical limits for DRAM, although the demonstration was a single cell.<ref>Kate McAlpine, [https://www.newscientist.com/channel/tech/dn14525-spin-flip-trick-points-to-fastest-ram-yet.html "Spin flip trick points to fastest RAM yet"], ''NewScientist'', 13 August 2008</ref> The differences compared to flash are far more significant, with write speeds as much as thousands of times faster. However, these speed comparisons are not for like-for-like current. High-density memory requires small transistors with reduced current, especially when built for low standby leakage. Under such conditions, write times shorter than 30&nbsp;ns may not be reached so easily. In particular, to meet solder reflow stability of 260&nbsp;°C over 90 seconds, 250&nbsp;ns pulses have been required.<ref>L. Thomas et al., S3S 2017</ref> This is related to the elevated thermal stability requirement driving up the write bit error rate. In order to avoid breakdown from higher current, longer pulses are needed.

For the perpendicular STT MRAM, the switching time is largely determined by the thermal stability Δ as well as the write current.<ref>{{cite journal |last1=Khvalkovskiy |first1=A.V. |last2=Apalkov |first2=D. |last3=Watts |first3=S.|last4=Chepulskii |first4=R.|last5=Beach |first5=R S.|last6=Ong |first6=A.|last7=Tang |first7=X.|last8=Driskill-Smith |first8=A.|last9=Butler |first9=W.H.|last10=Visscher |first10=P.B.|last11=Lottis |first11=D.|last12=Chen |first12=E.|last13=Nikitin |first13=V.|last14=Krounbi |first14=M.|title=Basic principles of STT-MRAM cell operation in memory arrays |journal=Journal of Physics D: Applied Physics |volume=46 |issue=7 |pages=074001 |year=2013 |doi=10.1088/0022-3727/46/7/074001 |bibcode=2013JPhD...46g4001K |s2cid=110519121 }}</ref> A larger Δ (better for data retention) would require a larger write current or a longer pulse. A combination of high speed and adequate retention is only possible with a sufficiently high write current.

The only current memory technology that easily competes with MRAM in terms of performance at comparable density is [[static random-access memory]] (SRAM). SRAM consists of a series of transistors arranged in a [[flip-flop (electronics)|flip-flop]], which will hold one of two states as long as power is applied. Since the transistors have a very low power requirement, their switching time is very low. However, since an SRAM cell consists of several transistors, typically four or six, its density is much lower than DRAM. This makes it expensive, which is why it is used only for small amounts of high-performance memory, notably the [[CPU cache]] in almost all modern [[central processing unit]] designs.

Although MRAM is not quite as fast as SRAM, it is close enough to be interesting even in this role. Given its much higher density, a CPU designer may be inclined to use MRAM to offer a much larger<!-- smaller? --> but somewhat slower cache, rather than a smaller<!-- larger? --> but faster one. It remains to be seen how this trade-off will play out in the future.