Editing NetBurst (section)

=== Execution Trace Cache ===
{{Main|Trace cache}}
Within the L1 cache of the CPU, Intel incorporated its Execution Trace Cache. It stores decoded [[micro-operation]]s, so that when executing a new instruction, instead of fetching and decoding the instruction again, the CPU directly accesses the decoded micro-ops from the trace cache, thereby saving considerable time. Moreover, the micro-ops are cached in their predicted path of execution, which means that when instructions are fetched by the CPU from the cache, they are already present in the correct order of execution.<ref>{{cite web |url=https://www.tomshardware.com/reviews/intel,264-6.html |title=Entering The Execution Pipeline - Pentium 4's Trace Cache, Continued |work=Intel's New Pentium 4 Processor |publisher=[[Tom's Hardware]] |date=November 20, 2000 |access-date=April 30, 2021}}</ref> Intel later introduced a similar but simpler concept with [[Sandy Bridge]] called [[micro-operation cache]] (UOP cache).