Editing Orthogonal instruction set (section)

==Orthogonality in practice==

===The PDP-11===
The PDP-11 was substantially orthogonal (primarily excepting its floating point instructions).<ref name=psych>{{cite web |url=http://www.psych.usyd.edu.au/pdp-11/intro.html |title= Introduction to the PDP-11 |website=University of Sydney}}</ref> Most integer instructions could operate on either 1-byte or 2-byte values and could access data stored in registers, stored as part of the instruction, stored in memory, or stored in memory and pointed to by addresses in registers or memory. Even the [[Program counter|PC]] and the [[stack (data structure)|stack]] [[pointer (computer programming)|pointer]] could be affected by the ordinary instructions using all of the ordinary data modes. "Immediate" mode (hardcoded numbers within an instruction, such as ADD #4, R1 (R1 = R1 + 4) was implemented as the mode "register indirect, autoincrement" and specifying the program counter (R7) as the register to use reference for indirection and to autoincrement. (Encoded as ADD (R7)+,R1 .word 4.)<ref name=tor>{{cite web |url=https://www.teach.cs.toronto.edu//~ajr/258/pdp11.pdf |title=PDP-11 instruction reference |website=University of Toronto}}</ref>

The PDP-11 used 3-bit fields for addressing modes (0-7) so there were (electronically) 8 addressing modes. An additional 3-bit field specified the registers (R0–R5, SP, PC). Immediate and absolute address operands applying the two autoincrement modes to the Program Counter (R7), provided a total of 10 conceptual addressing modes.  Most two operand instructions supported all addressing modes for both parameters.<ref name=tor/>

===The VAX-11===
The [[VAX|VAX-11]] extended the PDP-11's orthogonality to all data types, including floating point numbers.<ref name=arch>{{cite book |title= Computer Architecture: A Quantitative Approach |first1= John |last1=Hennessy |first2=David |last2=Patterson |page=151 |url=https://books.google.com/books?id=XX69oNsazH4C&pg=PA151|isbn= 9780080502526 |date= 2002-05-29 |publisher= Elsevier }}</ref> Instructions such as 'ADD' were divided into data-size dependent variants such as ADDB, ADDW, ADDL, ADDP, ADDF for add byte, word, longword, packed BCD and single-precision floating point, respectively. Like the PDP-11, the Stack Pointer and Program Counter were in the general register file (R14 and R15).<ref name=another>{{cite web |title=Another Approach to Instruction Set Architecture—VAX |url=https://minnie.tuhs.org/CompArch/Resources/webext3.pdf}}</ref>

The general form of a VAX-11 instruction would be:

 [[opcode]] [ [[operand]] ] [ [[operand]] ]  ...

Each component being one [[byte]], the opcode a value in the range 0–255, and each operand consisting of two [[nibble]]s, the upper 4 bits specifying an addressing mode, and the lower 4 bits (usually) specifying a register number (R0–R15).<ref name=another/>

In contrast to the PDP-11's 3-bit fields, the VAX-11's 4-bit sub-bytes resulted in 16 [[Addressing mode|addressing modes]] (0–15).  However, addressing modes 0–3 were "short immediate" for immediate data of 6 bits or less (the 2 low-order bits of the addressing mode being the 2 high-order bits of the immediate data, when prepended to the remaining 4 bits in that data-addressing byte).  Since addressing modes 0-3 were identical, this made 13 (electronic) addressing modes, but as in the PDP-11, the use of the Stack Pointer (R14) and Program Counter (R15) created a total of over 15 conceptual addressing modes (with the assembler program translating the source code into the actual stack-pointer or program-counter based addressing mode needed).<ref name=another/>

===The MC68000 and similar===
Motorola's designers attempted to make the assembly language orthogonal while the underlying machine language was somewhat less so. Unlike PDP-11, the MC68000 (68k) used separate registers to store data and the addresses of data in memory. The ISA was orthogonal to the extent that addresses could only be used in those registers, but there was no restriction on ''which'' of the registers could be used by different instructions. Likewise, the data registers were also orthogonal across instructions. Unlike the PDP-11, the 68000 only supported one general addressing mode for two-parameter instructions. The other parameter was always a register, with the exception of MOV. The MOV instructions supported all addressing modes for both parameters.<ref name=68k>{{cite book |title= The 68000 Microprocessor |first= Andrew |last=Veronis |page=54 |url=https://books.google.com/books?id=O2DTBwAAQBAJ&pg=PA54|isbn= 9781468466478 |date= 2012-12-06 |publisher= Springer }}</ref>

In contrast, the [[NS320xx]] series were originally designed as single-chip implementations of the VAX-11 ISA. Although this had to change due to legal issues, the resulting system retained much of the VAX-11's overall design philosophy and remained completely orthogonal.<ref name="tilson198310">{{cite news | url=https://archive.org/stream/byte-magazine-1983-10/1983_10_BYTE_08-10_UNIX#page/n267/mode/2up | title=Moving Unix to New Machines | work=BYTE | date=October 1983 | access-date=31 January 2015 | author=Tilson, Michael | pages=266}}</ref> This included the elimination of the separate data and address registers found in the 68k.<ref>{{cite web |url=http://www.datormuseum.se/home/chips/ns32532 |title= NS32532 |website=Datormuseum}}</ref>

===The 8080 and follow on designs===
The 8-bit [[Intel 8080]] (as well as the 8085 and 8051) microprocessor was basically a slightly extended accumulator-based design and therefore not orthogonal. An assembly-language programmer or compiler writer had to be mindful of which operations were possible on each register: Most 8-bit operations could be performed only on the 8-bit [[Accumulator (computing)|accumulator]] (the A-register), while 16-bit operations could be performed only on the 16-bit pointer/accumulator (the HL-register pair), whereas simple operations, such as increment, were possible on all seven 8-bit registers. This was largely due to a desire to keep all opcodes one byte long.

The [[binary-compatible]] [[Z80]] later added prefix-codes to escape from this 1-byte limit  and allow for a more powerful instruction set. The same basic idea was employed for the [[Intel 8086]], although, to allow for more radical extensions, ''binary''-compatibility with the 8080 was not attempted here. It maintained some degree of non-orthogonality for the sake of high code density at the time. The 32-bit extension of this architecture that was introduced with the [[80386]], was somewhat more orthogonal despite keeping all the 8086 instructions and their extended counterparts. However, the ''encoding-strategy'' used still shows many traces from the 8008 and 8080 (and Z80). For instance, single-byte encodings remain for certain frequent operations such as [[Stack (abstract data type)|push and pop]] of registers and constants; and the primary accumulator, the [[EAX register]], employs shorter encodings than the other registers on certain types of operations. Observations like this are sometimes exploited for [[code optimization]] in both compilers and hand written code.