Editing Peterson's algorithm (section)

==Note==
When working at the [[Computer hardware|hardware]] level, Peterson's algorithm is typically not needed to achieve atomic access. Most modern processors have special instructions, which, by locking the [[memory bus]], can be used to guarantee [[Atomicity (programming)|atomicity]] and provide [[mutual exclusion]] in [[Symmetric multiprocessing|SMP]] systems. Examples include [[test-and-set]] (<code>XCHG</code>) and [[compare-and-swap]] (<code>CMPXCHG</code>) on [[x86]] processors and [[load-link/store-conditional]] on [[DEC Alpha|Alpha]], [[MIPS architecture|MIPS]], [[PowerPC]], and other architectures. These instructions are intended to provide a way to build [[Synchronization (computer science)|synchronization]] primitives more efficiently than can be done with pure shared memory approaches.

Most modern CPUs reorder memory accesses to improve execution efficiency (see [[memory ordering]] for types of reordering allowed). Such processors invariably give some way to force ordering in a stream of memory accesses, typically through a [[memory barrier]] instruction. Implementation of Peterson's and related algorithms on processors that reorder memory accesses generally requires use of such operations to work correctly to keep sequential operations from happening in an incorrect order. Note that reordering of memory accesses can happen even on processors that don't reorder instructions (such as the [[PowerPC]] processor in the [[Xbox 360]]).{{Citation needed|date=May 2015}}