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Physical Address Extension
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=== 32-bit paging, 4 KiB pages, with PAE === [[File:X86 Paging PAE 4K.svg|400px|thumb|right|With PAE; 4 KB pages]] Enabling PAE (by setting bit 5, <code>PAE</code>, of the system register <code>CR4</code>) causes major changes to this scheme. By default, the size of each page remains as 4 KB. Each entry in the page table and page directory becomes 64 bits long (8 bytes), instead of 32 bits, to allow for additional address bits. However, the size of each table ''does not'' change, so both table and directory now have only 512 entries. Because this allows only one half of the entries of the original scheme, an extra level of hierarchy has been added, so the system register {{code|CR3}} now points physically to a ''Page Directory Pointer Table'', a short table containing four pointers to page directories. Supporting 64 bit addresses in the page-table is a significant change as this enables two changes to the processor addressing. Firstly, the page table walker, which uses physical addresses to access the page table and directory, can now access physical addresses greater than the 32-bit physical addresses supported in systems without PAE. From {{code|CR3}}, the page table walker can access page directories and tables that are beyond the 32-bit range. Secondly, the physical address for the data being accessed (stored in the page table) can be represented as a physical address larger than the 32-bit addresses supported in a system without PAE. Again, this allows data accesses to access physical memory regions beyond the 32-bit range.<ref name="Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, Chapter 4.4 Paging">{{cite book |title=Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A |chapter=4.4 Paging |url=https://www.intel.com/content/www/us/en/content-details/782158/intel-64-and-ia-32-architectures-software-developer-s-manual-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4.html?wapkw=intel%2064%20and%20ia-32%20architectures%20software%20developer%27s%20manual&docid=782161 |publisher=[[Intel]] |access-date=28 October 2023}}</ref>
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