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PowerPC 970
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==Northbridges== Two dedicated [[Northbridge (computing)|northbridges]] for PowerPC 970-based computers were manufactured by IBM: *CPC925{{snd}} Designed by Apple<ref>{{cite web|url=https://www.youtube.com/watch?v=iwsn27J_tlo |archive-url=https://ghostarchive.org/varchive/youtube/20211221/iwsn27J_tlo |archive-date=December 21, 2021 |url-status=live|title=WWDC 2003 Keynote |via=YouTube |author=Steve Jobs, Apple |date= June 25, 2003|access-date=October 16, 2009}}{{cbignore}}</ref> and called the ''U3'' or the ''U3H'' (which supports [[Error-correcting code|ECC]] memory). It is capable of supporting up to two PowerPC 970s or PowerPC 970FXs and has two 550 MHz unidirectional processor buses, a 400 MHz [[DDR SDRAM|DDR]] memory controller, x8 [[Accelerated Graphics Port|AGP]] and a 400 MHz 16-bit [[HyperTransport]] tunnel. It fabricated on a 130 nm process. Additionally, there was an unreleased U3Lite northbridge in development for the PowerBook G5, which never made it to market. *CPC945{{snd}} Designed by IBM and called ''U4'' by Apple, it is capable of supporting two PowerPC 970MPs and has two 625 MHz unidirectional processor buses, two memory controllers that support up to 64 GB of 533 MHz DDR2 SDRAM with ECC capability and has a x16 [[PCI Express|PCIe]] lane and an 800 MHz 16-bit HyperTransport tunnel. It is fabricated on a 90 nm process. A CPC965 northbridge was canceled. Slated for release in 2007, it was to be a uniprocessor-only northbridge. Its features were a 533 MHz DDR2 controller that supported up to 8 GB ECC memory, a 8x PCIe bus, integrated four-port [[Gigabit Ethernet]] with [[IPv4]] [[Transmission Control Protocol|TCP]]/[[User Datagram Protocol|UDP]] offloading, USB 2.0 ports, a [[Flash memory|Flash]]-interface. The northbridge contains an integrated [[PowerPC 400#PowerPC 405|PowerPC 405]] core to provide system management and configuration capabilities.<ref>LaPedus, Mark (March 10, 2006). [http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=193101381 "IBM rolls low-power processors, IP cores"] {{Webarchive|url=https://web.archive.org/web/20070926220729/http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=193101381 |date=September 26, 2007 }}. ''EE Times''.</ref>
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