Editing Programmable Array Logic (section)

==Programming PALs==
PALs were programmed electrically using binary patterns (as [[JEDEC]] [[ASCII]]/[[hexadecimal]] files) and a special electronic programming system available from either the manufacturer or a third party, such as [[Data I/O Corporation|DATA I/O]]. In addition to single-unit device programmers, device feeders and gang programmers were often used when more than just a few PALs needed to be programmed. (For large volumes, electrical programming costs could be eliminated by having the manufacturer fabricate a custom metal mask used to program the customers' patterns at the time of manufacture; MMI used the term "[[hard array logic]]" (HAL) to refer to devices programmed in this way.)

===Programming languages (by chronological order of appearance) ===
[[File:PALASM Design.jpg|thumb|PALASM design of a 4-bit [[Counter (digital)|counter]]]]
Though some engineers programmed PAL devices by manually editing files containing the binary fuse pattern data, most opted to design their logic using a [[hardware description language]] (HDL) such as Data I/O's [[Advanced Boolean Expression Language|ABEL]], Logical Devices' CUPL, or MMI's [[PALASM]]. These were [[computer-assisted design]] ([[Computer-aided design|CAD]]) (now referred to as "[[electronic design automation]]") programs which translated (or "compiled") the designers' logic equations into binary fuse map files used to program (and often test) each device.

====PALASM====
The [[PALASM]] (from "PAL assembler") language was developed by [[John Birkner]] in the early 1980s and the PALASM compiler was written by MMI in FORTRAN IV on an IBM 370/168. MMI made the source code available to users at no cost. By 1983, MMI customers ran versions on the [[Digital Equipment Corporation|DEC]] [[PDP-11]], [[Data General Nova|Data General NOVA]], [[Hewlett-Packard]] [[HP 2100]], [[MDS800]] and others.

It was used to express Boolean equations for the output pins in a text file, which was then converted to the 'fuse map' file for the programming system using a vendor-supplied program; later the option of translation from schematics became common, and later still, 'fuse maps' could be 'synthesized' from an [[hardware description language|HDL]] (hardware description language) such as [[Verilog]].

====CUPL====
Assisted Technology released CUPL ('''C'''ompiler for '''U'''niversal '''P'''rogrammable '''L'''ogic) in September 1983.<ref name="Alford 1989">{{cite book |last=Alford |first=Roger C.| title=Programmable Logic Designer's Guide |publisher=Howard W. Sams| date=1989 |pages=14–15, 166–168 |isbn =0-672-22575-1 |quote=In 1981, [Bob] Osann started Assisted Technology to develop PLD support tools. In September 1983 Assisted Technology released version 1.01a of its CUPL (Universal Compiler for Programmable Logic) PLD compiler, supporting 29 devices.}}</ref> The software was always referred to as CUPL and never the expanded acronym. It was the first commercial design tool that supported multiple PLD families. The initial release was for the IBM PC and MS-DOS, but it was written in the [[C (programming language)|C programming language]] so it could be ported to additional platforms.<ref name="CUPL Datasheet 1983">{{cite press release |title=CUPL - The Universal Language For Programmable Logic |publisher=Assisted Technology, Inc. |location=San Jose, CA |date=1983 |url=http://www.swtpc.com/mholley/PLD_History/ABEL_project/CUPL_Data_Sheet_1983_ocr.pdf |access-date=2013-08-10 |archive-url=https://web.archive.org/web/20131029195406/http://www.swtpc.com/mholley/PLD_History/ABEL_project/CUPL_Data_Sheet_1983_ocr.pdf |archive-date=2013-10-29 |url-status=dead}} An early 1983 pre-release datasheet for CUPL.</ref> Assisted Technology was acquired by Personal CAD Systems (P-CAD) in July 1985. In 1986, PCAD's schematic capture package could be used as a front end for CUPL.<ref name="PCAD 1985">{{cite journal| title=Personal CAD Systems |journal=Computer World |volume=19 |issue=29 |page =97 |publisher=CW Communications |location=Framingham, MA |date=July 22, 1985| url=https://books.google.com/books?id=6mxHXqXKdFMC&pg=PA97| issn=0010-4841}}</ref> CUPL was later acquired by Logical Devices and is now owned by [[Altium]].<ref name="CUPL trademark">US Patent and Trademark Office. "CUPL" Computer software, namely, software used to develop and compile designs for programmable logic devices, and related user manuals distributed therewith. First used in 1983, status Active. Serial Number 76357007. Registration Number 2909461. Owner: Altium Limited, Australia 3 Minna Close, Belrose NSW2085, Australia.</ref> CUPL is currently available as an integrated development package for Microsoft Windows.<ref name="CUBEL">{{cite web |title=CUBEL ChipDesigner 5.0 |publisher=Logical Devices |date=August 2013 |url=http://www.logicaldevices.com/cubel.htm |archive-url=https://web.archive.org/web/20150529134635/http://www.logicaldevices.com:80/cubel.htm |archive-date=May 29, 2015 |url-status=dead}}</ref>

[[Atmel]] releases for free [http://www.atmel.com/tools/WINCUPL.aspx WinCUPL] (their own design software for all Atmel SPLDs and CPLDs). Atmel was acquired by Microchip in 2016.

====ABEL====
[[Data I/O Corporation]] released [[Advanced Boolean Expression Language|ABEL]] in April, 1984. The development team was Michael Holley, Mike Mraz, Gerrit Barrere, [[Walter Bright]], Bjorn Freeman-Benson, Kyu Lee, David Pellerin, Mary Bailey, Daniel Burrier and Charles Olivier.

Data I/O spun off the ABEL product line into an electronic design automation company called Synario Design Systems and then sold Synario to MINC Inc in 1997.
MINC was focused on developing FPGA development tools. The company closed its doors in 1998 and Xilinx acquired some of MINC's assets including the ABEL language and tool set. ABEL then became part of the Xilinx Webpack tool suite.
Now Xilinx owns ABEL.

===Device programmers===
Popular device programmers included [[Data I/O Corporation]]'s Model 60A Logic Programmer and Model 2900.

One of the first PAL programmers was the Structured Design SD20/24. They had the PALASM software built-in and only required a CRT terminal to enter the equations and view the fuse plots. After fusing, the outputs of the PAL could be verified if test vectors were entered in the source file.