Editing Protected mode (section)

== Features ==

Protected mode has a number of features designed to enhance an operating system's control over application software, in order to increase security and system stability.<ref name="Purpose of protected mode" /> These additions allow the operating system to function in a way that would be significantly more difficult or even impossible without proper hardware support.<ref name="Multitasking">{{ cite book | title = Intel 80386 Programmer's Reference Manual 1986 | url = http://bitsavers.org/components/intel/80386/230985-001_80386_Programmers_Reference_Manual_1986.pdf | date = 1986 | publisher = Intel | location = Santa Clara, CA | at = Chapter 7, Multitasking }}</ref>

=== Privilege levels ===
{{details|Ring (computer security)}}
[[File:Priv rings.svg|thumb|right|300px|Example of privilege ring usage in an operating system using all rings]]

In protected mode, there are four privilege levels or [[ring (computer security)|ring]]s, numbered from 0 to 3, with ring 0 being the most privileged and 3 being the least. The use of rings allows for system software to restrict tasks from accessing data, [[call gate]]s or executing privileged instructions.<ref name="Rings">{{ cite book | title = Intel 64 and IA-32 Architectures Software Developer's Manual Volume 1: Basic Architecture | publisher = [[Intel]] | at = Section 6.3.5 Calls to Other Privilege Levels |date=May 2019 | url = https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-software-developers-manual-volume-1-basic-architecture }}</ref> In most environments, the operating system and some [[device driver]]s run in ring 0 and applications run in ring 3.<ref name="Rings"/>

=== Real mode application compatibility ===

According to the ''Intel 80286 Programmer's Reference Manual'',<ref name="286 compatibility">{{ cite book | title = 80286 and 80287 Programmer's Reference Manual | url = http://bitsavers.org/components/intel/80286/210498-005_80286_and_80287_Programmers_Reference_Manual_1987.pdf | date = 1987 | publisher = Intel | location = Santa Clara, CA | at = Section 1.2 Modes of Operation }}</ref>

{{ quote
| the 80286 remains upwardly compatible with most 8086 and 80186 application programs. Most 8086 application programs can be re-compiled or re-assembled and executed on the 80286 in Protected Mode.
}}

For the most part, the binary compatibility with real-mode code, the ability to access up to 16 MB of physical memory, and 1 GB of [[virtual memory]], were the most apparent changes to application programmers.<ref name="286 programmer ref">{{ cite book | title = 80286 and 80287 Programmer's Reference Manual | url = http://bitsavers.org/components/intel/80286/210498-005_80286_and_80287_Programmers_Reference_Manual_1987.pdf | date = 1987 | publisher = Intel | location = Santa Clara, California | at = Section 1.3.1 Memory Management }}</ref> This was not without its limitations. If an application utilized or relied on any of the techniques below, it would not run:<ref name="Compatibility limitations">{{ cite book | title = 80286 and 80287 Programmer's Reference Manual | url = http://bitsavers.org/components/intel/80286/210498-005_80286_and_80287_Programmers_Reference_Manual_1987.pdf | date = 1987 | publisher = Intel | location = Santa Clara, California | at = Appendix C 8086/8088 Compatibility Considerations }}</ref>

* Segment arithmetic
* Privileged instructions
* Direct hardware access
* [[Self-modifying code|Writing to a code segment]]
* Executing data
* Overlapping segments
* Use of BIOS functions, due to the BIOS interrupts being reserved by Intel<ref name="BIOS only available through workarounds">{{ cite web | url = http://www.freepatentsonline.com/6105101.html | title = Memory access control method and system for realizing the same | work = US Patent 5483646 | access-date = 2007-07-25 | date = May 6, 1998 | format = Patent | quote = This has been impossible to-date and has forced BIOS development teams to add support into the BIOS for 32 bit function calls from 32 bit applications. }}</ref>

In reality, almost all [[DOS]] application programs violated these rules.<ref name="Incompatibilities">{{ cite web | url = http://osdev.berlios.de/v86.html | title = Virtual 8086 Mode | access-date = 2007-07-25 | last = Robinson | first = Tim | date = August 26, 2002 | format = Guide | publisher = berliOS | quote = ...&nbsp;secondly, protected mode was also incompatible with the vast amount of real-mode code around at the time. | url-status = dead | archive-url = https://web.archive.org/web/20021003235610/http://osdev.berlios.de/v86.html | archive-date = October 3, 2002 }}</ref> Due to these limitations, [[virtual 8086 mode]] was introduced with the 386. Despite such potential setbacks, [[Windows 3.0]] and its successors can take advantage of the binary compatibility with real mode to run many Windows 2.x ([[Windows 2.0]] and [[Windows 2.1x]]) applications in protected mode, which ran in real mode in Windows 2.x.<ref name="Windows protected mode usage">{{ cite web | url = http://osdev.berlios.de/v86.html | title = Virtual 8086 Mode | access-date = 2007-07-25 | last = Robinson | first = Tim | date = August 26, 2002 | format = Guide | publisher = berliOS | url-status = dead | archive-url = https://web.archive.org/web/20021003235610/http://osdev.berlios.de/v86.html | archive-date = October 3, 2002 }}</ref>

=== Virtual 8086 mode ===
{{main|Virtual 8086 mode}}

With the release of the 386, protected mode offers what the Intel manuals call ''virtual 8086 mode''. Virtual 8086 mode is designed to allow code previously written for the 8086 to run unmodified and concurrently with other tasks, without compromising security or system stability.<ref name="V8086 mode">{{ cite book | title = Intel 64 and IA-32 Architectures Software Developer's Manual Combined Volumes 3A, 3B, 3C, and 3D: System Programming Guide | publisher = [[Intel]] | at = Section 20.2 Virtual 8086 Mode |date=May 2019 | url = https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-3a-3b-3c-and-3d-system-programming-guide }}</ref>

Virtual 8086 mode, however, is not completely backward compatible with all programs. Programs that require segment manipulation, privileged instructions, direct hardware access, or use [[self-modifying code]] will generate an [[exception handling|exception]] that must be served by the operating system.<ref name="V8086 limitations">{{ cite book | title = Intel 64 and IA-32 Architectures Software Developer's Manual Combined Volumes 3A, 3B, 3C, and 3D: System Programming Guide | publisher = [[Intel]] | at = Section 20.2.7 Sensitive Instructions |date=May 2019| url = https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-3a-3b-3c-and-3d-system-programming-guide }}</ref> In addition, applications running in virtual 8086 mode generate a [[trap (computing)|trap]] with the use of instructions that involve [[input/output]] (I/O), which can negatively impact performance.<ref name="V86 performance">{{ cite web | url = http://osdev.berlios.de/v86.html | title = Virtual 8086 Mode | access-date = 2007-07-25 | last = Robinson | first = Tim | date = August 26, 2002 | format = Guide | publisher = berliOS | quote = A downside to using V86 mode is speed: every IOPL-sensitive instruction will cause the CPU to trap to kernel mode, as will I/O to ports which are masked out in the TSS. | url-status = dead | archive-url = https://web.archive.org/web/20021003235610/http://osdev.berlios.de/v86.html | archive-date = October 3, 2002 }}</ref>

Due to these limitations, some programs originally designed to run on the 8086 cannot be run in virtual 8086 mode. As a result, system software is forced to either compromise system security or backward compatibility when dealing with [[legacy system|legacy software]]. An example of such a compromise can be seen with the release of [[Windows NT]], which dropped backward compatibility for "ill-behaved" DOS applications.<ref name="DOS and NT">{{cite book | last = Dabak | first = Prasad |author2=Millind Borate  | title = Undocumented Windows NT | type = Book |date=October 1999 | publisher = Hungry Minds | isbn = 0-7645-4569-8}}</ref>

=== Segment addressing ===
{{details|X86 memory segmentation}}
[[File:080810-protected-286-segments.PNG|thumb|right|upright=1.4|Virtual segments of 80286]]

==== Real mode ====
In real mode each logical address points directly into a physical memory location, every logical address consists of two 16-bit parts: The segment part of the logical address contains the base address of a segment with a granularity of 16 bytes, i.e. a segment may start at physical address 0, 16, 32,&nbsp;..., 2<sup>20</sup>&nbsp;−&nbsp;16. The offset part of the logical address contains an offset inside the segment, i.e. the physical address can be calculated as physical_address = segment_part × 16 + offset, if the address [[A20 line|line A20]] is enabled, or (segment_part × 16 + offset) mod 2<sup>20</sup>, if A20 is off.{{Clarify|date=August 2011}} Every segment has a size of 2<sup>16</sup>&nbsp;bytes.

==== Protected mode ====
In protected mode, the {{Mono|segment_part}} is replaced by a 16-bit ''selector'', in which the 13 upper bits (bit 3 to bit 15) contain the index of an ''entry'' inside a ''descriptor table''. The next bit (bit 2) specifies whether the operation is used with the GDT or the LDT. The lowest two bits (bit 1 and bit 0) of the selector are combined to define the privilege of the request, where the values of 0 and 3 represent the highest and the lowest privilege, respectively.  This means that the byte offset of descriptors in the descriptor table is the same as the 16-bit selector, provided the lower three bits are zeroed.

The descriptor table entry defines the real ''linear'' address of the segment, a limit value for the segment size, and some attribute bits (flags).

==== 286 ====
The segment address inside the descriptor table entry has a length of 24 bits so every byte of the physical memory can be defined as bound of the segment. The limit value inside the descriptor table entry has a length of 16 bits so segment length can be between 1 byte and 2<sup>16</sup> byte. The calculated linear address equals the physical memory address.

==== 386 ====
The segment address inside the descriptor table entry is expanded to 32 bits so every byte of the physical memory can be defined as bound of the segment. The limit value inside the descriptor table entry is expanded to 20 bits and completed with a granularity flag (G-bit, for short):

* If G-bit is zero limit has a granularity of 1 byte, i.e. segment size may be 1, 2, ..., 2<sup>20</sup> bytes.
* If G-bit is one limit has a granularity of 2<sup>12</sup> bytes, i.e. segment size may be 1 × 2<sup>12</sup>, 2 × 2<sup>12</sup>, ..., 2<sup>20</sup> × 2<sup>12</sup> bytes. If paging is off, the calculated linear address equals the physical memory address. If paging is on, the calculated linear address is used as input of paging.

The 386 processor also uses 32 bit values for the address offset.

For maintaining compatibility with 286 protected mode a new default flag (D-bit, for short) was added. If the D-bit of a code segment is off (0) all commands inside this segment will be interpreted as 16-bit commands by default; if it is on (1), they will be interpreted as 32-bit commands.

==== Structure of segment descriptor entry ====
<div>
{| class="infobox" style="text-align:center"
|-
|style="text-align:center" |''80286 Segment descriptor''
|-
|
{|
|style="width:15px;text-align:center"|<sup>3</sup><sub>1</sub>
|style="width:15px;text-align:center"|<sup>3</sup><sub>0</sub>
|style="width:15px;text-align:center"|<sup>2</sup><sub>9</sub>
|style="width:15px;text-align:center"|<sup>2</sup><sub>8</sub>
|style="width:15px;text-align:center"|<sup>2</sup><sub>7</sub>
|style="width:15px;text-align:center"|<sup>2</sup><sub>6</sub>
|style="width:15px;text-align:center"|<sup>2</sup><sub>5</sub>
|style="width:15px;text-align:center"|<sup>2</sup><sub>4</sub>
|style="width:15px;text-align:center"|<sup>2</sup><sub>3</sub>
|style="width:15px;text-align:center"|<sup>2</sup><sub>2</sub>
|style="width:15px;text-align:center"|<sup>2</sup><sub>1</sub>
|style="width:15px;text-align:center"|<sup>2</sup><sub>0</sub>
|style="width:15px;text-align:center"|<sup>1</sup><sub>9</sub>
|style="width:15px;text-align:center"|<sup>1</sup><sub>8</sub>
|style="width:15px;text-align:center"|<sup>1</sup><sub>7</sub>
|style="width:15px;text-align:center"|<sup>1</sup><sub>6</sub>
|style="width:15px;text-align:center"|<sup>1</sup><sub>5</sub>
|style="width:15px;text-align:center"|<sup>1</sup><sub>4</sub>
|style="width:15px;text-align:center"|<sup>1</sup><sub>3</sub>
|style="width:15px;text-align:center"|<sup>1</sup><sub>2</sub>
|style="width:15px;text-align:center"|<sup>1</sup><sub>1</sub>
|style="width:15px;text-align:center"|<sup>1</sup><sub>0</sub>
|style="width:15px;text-align:center"|<sup>0</sup><sub>9</sub>
|style="width:15px;text-align:center"|<sup>0</sup><sub>8</sub>
|style="width:15px;text-align:center"|<sup>0</sup><sub>7</sub>
|style="width:15px;text-align:center"|<sup>0</sup><sub>6</sub>
|style="width:15px;text-align:center"|<sup>0</sup><sub>5</sub>
|style="width:15px;text-align:center"|<sup>0</sup><sub>4</sub>
|style="width:15px;text-align:center"|<sup>0</sup><sub>3</sub>
|style="width:15px;text-align:center"|<sup>0</sup><sub>2</sub>
|style="width:15px;text-align:center"|<sup>0</sup><sub>1</sub>
|style="width:15px;text-align:center"|<sup>0</sup><sub>0</sub>
|-
|colspan="16" style="background:silver;text-align:center"|Base[0..15]
|colspan="16" style="background:silver;text-align:center"|Limit[0..15]
|-
|style="width:15px;text-align:center"|<sup>6</sup><sub>3</sub>
|style="width:15px;text-align:center"|<sup>6</sup><sub>2</sub>
|style="width:15px;text-align:center"|<sup>6</sup><sub>1</sub>
|style="width:15px;text-align:center"|<sup>6</sup><sub>0</sub>
|style="width:15px;text-align:center"|<sup>5</sup><sub>9</sub>
|style="width:15px;text-align:center"|<sup>5</sup><sub>8</sub>
|style="width:15px;text-align:center"|<sup>5</sup><sub>7</sub>
|style="width:15px;text-align:center"|<sup>5</sup><sub>6</sub>
|style="width:15px;text-align:center"|<sup>5</sup><sub>5</sub>
|style="width:15px;text-align:center"|<sup>5</sup><sub>4</sub>
|style="width:15px;text-align:center"|<sup>5</sup><sub>3</sub>
|style="width:15px;text-align:center"|<sup>5</sup><sub>2</sub>
|style="width:15px;text-align:center"|<sup>5</sup><sub>1</sub>
|style="width:15px;text-align:center"|<sup>5</sup><sub>0</sub>
|style="width:15px;text-align:center"|<sup>4</sup><sub>9</sub>
|style="width:15px;text-align:center"|<sup>4</sup><sub>8</sub>
|style="width:15px;text-align:center"|<sup>4</sup><sub>7</sub>
|style="width:15px;text-align:center"|<sup>4</sup><sub>6</sub>
|style="width:15px;text-align:center"|<sup>4</sup><sub>5</sub>
|style="width:15px;text-align:center"|<sup>4</sup><sub>4</sub>
|style="width:15px;text-align:center"|<sup>4</sup><sub>3</sub>
|style="width:15px;text-align:center"|<sup>4</sup><sub>2</sub>
|style="width:15px;text-align:center"|<sup>4</sup><sub>1</sub>
|style="width:15px;text-align:center"|<sup>4</sup><sub>0</sub>
|style="width:15px;text-align:center"|<sup>3</sup><sub>9</sub>
|style="width:15px;text-align:center"|<sup>3</sup><sub>8</sub>
|style="width:15px;text-align:center"|<sup>3</sup><sub>7</sub>
|style="width:15px;text-align:center"|<sup>3</sup><sub>6</sub>
|style="width:15px;text-align:center"|<sup>3</sup><sub>5</sub>
|style="width:15px;text-align:center"|<sup>3</sup><sub>4</sub>
|style="width:15px;text-align:center"|<sup>3</sup><sub>3</sub>
|style="width:15px;text-align:center"|<sup>3</sup><sub>2</sub>
|-
|colspan="16" style="background:silver;text-align:center"|''Unused''
|colspan="1" style="background:silver;text-align:center"|P
|colspan="2" style="background:silver;text-align:center"|DPL
|colspan="1" style="background:silver;text-align:center"|S
|colspan="1" style="background:silver;text-align:center"|X
|colspan="1" style="background:silver;text-align:center"|C
|colspan="1" style="background:silver;text-align:center"|R
|colspan="1" style="background:silver;text-align:center"|A
|colspan="8" style="background:silver;text-align:center"|Base[16..23]
|}
|}

{| class="infobox" style="text-align:center"
|-
|style="text-align:center" |''80386 Segment descriptor''
|-
|
{| style="text-align:center"
|style="width:15px;text-align:center"|<sup>3</sup><sub>1</sub>
|style="width:15px;text-align:center"|<sup>3</sup><sub>0</sub>
|style="width:15px;text-align:center"|<sup>2</sup><sub>9</sub>
|style="width:15px;text-align:center"|<sup>2</sup><sub>8</sub>
|style="width:15px;text-align:center"|<sup>2</sup><sub>7</sub>
|style="width:15px;text-align:center"|<sup>2</sup><sub>6</sub>
|style="width:15px;text-align:center"|<sup>2</sup><sub>5</sub>
|style="width:15px;text-align:center"|<sup>2</sup><sub>4</sub>
|style="width:15px;text-align:center"|<sup>2</sup><sub>3</sub>
|style="width:15px;text-align:center"|<sup>2</sup><sub>2</sub>
|style="width:15px;text-align:center"|<sup>2</sup><sub>1</sub>
|style="width:15px;text-align:center"|<sup>2</sup><sub>0</sub>
|style="width:15px;text-align:center"|<sup>1</sup><sub>9</sub>
|style="width:15px;text-align:center"|<sup>1</sup><sub>8</sub>
|style="width:15px;text-align:center"|<sup>1</sup><sub>7</sub>
|style="width:15px;text-align:center"|<sup>1</sup><sub>6</sub>
|style="width:15px;text-align:center"|<sup>1</sup><sub>5</sub>
|style="width:15px;text-align:center"|<sup>1</sup><sub>4</sub>
|style="width:15px;text-align:center"|<sup>1</sup><sub>3</sub>
|style="width:15px;text-align:center"|<sup>1</sup><sub>2</sub>
|style="width:15px;text-align:center"|<sup>1</sup><sub>1</sub>
|style="width:15px;text-align:center"|<sup>1</sup><sub>0</sub>
|style="width:15px;text-align:center"|<sup>0</sup><sub>9</sub>
|style="width:15px;text-align:center"|<sup>0</sup><sub>8</sub>
|style="width:15px;text-align:center"|<sup>0</sup><sub>7</sub>
|style="width:15px;text-align:center"|<sup>0</sup><sub>6</sub>
|style="width:15px;text-align:center"|<sup>0</sup><sub>5</sub>
|style="width:15px;text-align:center"|<sup>0</sup><sub>4</sub>
|style="width:15px;text-align:center"|<sup>0</sup><sub>3</sub>
|style="width:15px;text-align:center"|<sup>0</sup><sub>2</sub>
|style="width:15px;text-align:center"|<sup>0</sup><sub>1</sub>
|style="width:15px;text-align:center"|<sup>0</sup><sub>0</sub>
|-
|colspan="16" style="background:silver;text-align:center"|Base[0..15]
|colspan="16" style="background:silver;text-align:center"|Limit[0..15]
|-
|style="width:15px;text-align:center"|<sup>6</sup><sub>3</sub>
|style="width:15px;text-align:center"|<sup>6</sup><sub>2</sub>
|style="width:15px;text-align:center"|<sup>6</sup><sub>1</sub>
|style="width:15px;text-align:center"|<sup>6</sup><sub>0</sub>
|style="width:15px;text-align:center"|<sup>5</sup><sub>9</sub>
|style="width:15px;text-align:center"|<sup>5</sup><sub>8</sub>
|style="width:15px;text-align:center"|<sup>5</sup><sub>7</sub>
|style="width:15px;text-align:center"|<sup>5</sup><sub>6</sub>
|style="width:15px;text-align:center"|<sup>5</sup><sub>5</sub>
|style="width:15px;text-align:center"|<sup>5</sup><sub>4</sub>
|style="width:15px;text-align:center"|<sup>5</sup><sub>3</sub>
|style="width:15px;text-align:center"|<sup>5</sup><sub>2</sub>
|style="width:15px;text-align:center"|<sup>5</sup><sub>1</sub>
|style="width:15px;text-align:center"|<sup>5</sup><sub>0</sub>
|style="width:15px;text-align:center"|<sup>4</sup><sub>9</sub>
|style="width:15px;text-align:center"|<sup>4</sup><sub>8</sub>
|style="width:15px;text-align:center"|<sup>4</sup><sub>7</sub>
|style="width:15px;text-align:center"|<sup>4</sup><sub>6</sub>
|style="width:15px;text-align:center"|<sup>4</sup><sub>5</sub>
|style="width:15px;text-align:center"|<sup>4</sup><sub>4</sub>
|style="width:15px;text-align:center"|<sup>4</sup><sub>3</sub>
|style="width:15px;text-align:center"|<sup>4</sup><sub>2</sub>
|style="width:15px;text-align:center"|<sup>4</sup><sub>1</sub>
|style="width:15px;text-align:center"|<sup>4</sup><sub>0</sub>
|style="width:15px;text-align:center"|<sup>3</sup><sub>9</sub>
|style="width:15px;text-align:center"|<sup>3</sup><sub>8</sub>
|style="width:15px;text-align:center"|<sup>3</sup><sub>7</sub>
|style="width:15px;text-align:center"|<sup>3</sup><sub>6</sub>
|style="width:15px;text-align:center"|<sup>3</sup><sub>5</sub>
|style="width:15px;text-align:center"|<sup>3</sup><sub>4</sub>
|style="width:15px;text-align:center"|<sup>3</sup><sub>3</sub>
|style="width:15px;text-align:center"|<sup>3</sup><sub>2</sub>
|-
|colspan="8" style="background:silver;text-align:center"|Base[24..31]
|colspan="1" style="background:silver;text-align:center"|G
|colspan="1" style="background:silver;text-align:center"|D
|colspan="1" style="background:silver;text-align:center"|0
|colspan="1" style="background:silver;text-align:center"|''U''
|colspan="4" style="background:silver;text-align:center"|Limit[16..19]
|colspan="1" style="background:silver;text-align:center"|P
|colspan="2" style="background:silver;text-align:center"|DPL
|colspan="1" style="background:silver;text-align:center"|S
|colspan="1" style="background:silver;text-align:center"|X
|colspan="1" style="background:silver;text-align:center"|C
|colspan="1" style="background:silver;text-align:center"|R
|colspan="1" style="background:silver;text-align:center"|A
|colspan="8" style="background:silver;text-align:center"|Base[16..23]
|}
|}

Where:
*''A'' is the ''Accessed'' bit;
*''R'' is the ''Readable'' bit;
*''C'' (Bit 42) depends on ''X'':<ref name="OSDev GDT">{{cite web|url=https://wiki.osdev.org/Global_Descriptor_Table#Structure|title=Global Descriptor table - OSDev Wiki}}</ref>
**if ''X'' = 1 then ''C'' is the ''Conforming'' bit, and determines which privilege levels can far-jump to this segment (without changing privilege level):
***if ''C'' = 0 then only code with the same privilege level as ''DPL'' may jump here;
***if ''C'' = 1 then code with the same or a lower privilege level relative to ''DPL'' may jump here.
**if ''X'' = 0 then ''C'' is the ''direction'' bit:
***if ''C'' = 0 then the segment grows ''up'';
***if ''C'' = 1 then the segment grows ''down''.
*''X'' is the ''Executable'' bit:<ref name="OSDev GDT"/>
**if ''X'' = 1 then the segment is a code segment;
**if ''X'' = 0 then the segment is a data segment.
*''S'' is the ''Segment type'' bit, which should generally be cleared for system segments;<ref name="OSDev GDT"></ref>
*''DPL'' is the ''Descriptor Privilege Level'';
*''P'' is the ''Present'' bit;
*''D'' is the ''Default operand size'';
*''G'' is the ''Granularity'' bit;
*Bit 52 of the 80386 descriptor is not used by the hardware.
</div>

=== Paging ===
{{details|Paging}}
[[File:Virtual address space and physical address space relationship.svg|thumb|Common method of using paging to create a virtual address space]]
[[File:080810-protected-386-paging.svg|thumb|Paging (on Intel 80386) with page size of 4K]]

In addition to adding virtual 8086 mode, the 386 also added paging to protected mode.<ref name="paging introduced">{{ cite web | url = http://www.deinmeister.de/x86modes.htm#c1 | title = ProtectedMode overview [deinmeister.de] | access-date = 2007-07-29 | format = Website }}</ref> Through paging, system software can restrict and control a task's access to pages, which are sections of memory. In many operating systems, paging is used to create an independent virtual address space for each task, preventing one task from manipulating the memory of another. Paging also allows for pages to be moved out of [[primary storage]] and onto a slower and larger [[secondary storage]], such as a [[hard disk drive]].<ref name="Paging usage">{{cite web | url = http://technet2.microsoft.com/windowsserver/en/library/efc41320-713f-4004-bc81-ddddfc8552651033.mspx?mfr=true | title = What Is PAE X86? | access-date = 2007-07-29 | date = May 28, 2003 | format = Article | publisher = Microsoft TechNet | quote = The paging process allows the operating system to overcome the real physical memory limits. However, it also has a direct impact on performance because of the time necessary to write or retrieve data from disk. | archive-date = 2008-04-22 | archive-url = https://web.archive.org/web/20080422184656/http://technet2.microsoft.com/windowsserver/en/library/efc41320-713f-4004-bc81-ddddfc8552651033.mspx?mfr=true | url-status = dead }}</ref> This allows for more memory to be used than physically available in primary storage.<ref name="Paging usage" />

The x86 architecture allows control of pages through two [[array data structure|array]]s: page directories and [[page table]]s. Originally, a page directory was the size of one page, four kilobytes, and contained 1,024 page directory entries (PDE), although subsequent enhancements to the x86 architecture have added the ability to use larger page sizes. Each PDE contained a [[pointer (computer programming)|pointer]] to a page table. A page table was also originally four kilobytes in size and contained 1,024 page table entries (PTE). Each PTE contained a pointer to the actual page's physical address and are only used when the four-kilobyte pages are used. At any given time, only one page directory may be in active use.<ref name="Only one page directory">{{cite web | url = http://www.embedded.com/98/9806fe2.htm | title = Advanced Embedded x86 Programming: Paging | access-date = 2007-07-29 | last = Gareau | first = Jean | format = Guide | publisher = Embedded.com | quote = Only one page directory may be active at a time, indicated by the CR3 register. | archive-date = 2008-05-16 | archive-url = https://web.archive.org/web/20080516202434/http://www.embedded.com/98/9806fe2.htm | url-status = dead }}</ref>

=== Multitasking ===
{{details|Computer multitasking}}

Through the use of the rings, privileged [[call gate]]s, and the [[Task State Segment]] (TSS), introduced with the 286, [[preemptive multitasking]] was made possible on the x86 architecture. The TSS allows general-purpose registers, segment selector fields, and stacks to all be modified without affecting those of another task. The TSS also allows a task's privilege level, and I/O port permissions to be independent of another task's.

In many operating systems, the full features of the TSS are not used.<ref name="TSS Usage">{{ cite web | url = http://neworder.box.sk/newsread.php?newsid=10562 | work = NewOrer | title = news: Multitasking for x86 explained #1 | access-date = 2007-07-29 | author = zwanderer | date = May 2, 2004 | format = Article | publisher = NewOrder | quote = The reason why software task switching is so popular is that it can be faster than hardware task switching. Intel never actually developed the hardware task switching, they implemented it, saw that it worked, and just left it there. Advances in multitasking using software have made this form of task switching faster (some say up to 3 times faster) than the hardware method. Another reason is that the Intel way of switching tasks isn't portable at all | archive-url = https://web.archive.org/web/20070212161434/http://neworder.box.sk/newsread.php?newsid=10562 | archive-date = 2007-02-12 }}</ref> This is commonly due to portability concerns or due to the performance issues created with hardware task switches.<ref name="TSS Usage" /> As a result, many operating systems use both hardware and software to create a multitasking system.<ref name="Uses both">{{ cite web | url = http://neworder.box.sk/newsread.php?newsid=10562 | work = NewOrer | title = news: Multitasking for x86 explained #1 | access-date = 2007-07-29 | author = zwanderer | date = May 2, 2004 | format = Article | publisher = NewOrder | quote = ...&nbsp;both rely on the Intel processors ability to switch tasks, they rely on it in different ways. | archive-url = https://web.archive.org/web/20070212161434/http://neworder.box.sk/newsread.php?newsid=10562 | archive-date = 2007-02-12 }}</ref>