Editing Translation lookaside buffer (section)

=={{anchor|PCID}}Address-space switch==
On an address-space switch, as occurs when [[Context switch|context switching]] between processes (but not between threads), some TLB entries can become invalid, since the virtual-to-physical mapping is different. The simplest strategy to deal with this is to completely flush the TLB. This means that after a switch, the TLB is empty, and ''any'' memory reference will be a miss, so it will be some time before things are running back at full speed. Newer CPUs use more effective strategies marking which process an entry is for. This means that if a second process runs for only a short time and jumps back to a first process, the TLB may still have valid entries, saving the time to reload them.<ref>{{cite news |author=Ulrich Drepper |date=9 October 2014 |title=Memory part 3: Virtual Memory |publisher=[[LWN.net]] |url=https://lwn.net/Articles/253361/ }}</ref>

Other strategies avoid flushing the TLB on a context switch:
(a) A [[single address space operating system]] uses the same virtual-to-physical mapping for all processes.
(b) Some CPUs have a process ID register, and the hardware uses TLB entries only if they match the current process ID.

For example, in the [[Alpha 21264]], each TLB entry is tagged with an ''address space number'' (ASN), and only TLB entries with an ASN matching the current task are considered valid. For another example, in the [[Intel Pentium Pro]], the page global enable (PGE) flag in the register [[Control register#CR4|CR4]] and the global (G) flag of a page-directory or page-table entry can be used to prevent frequently used pages from being automatically invalidated in the TLBs on a task switch or a load of register CR3. Since the 2010 [[Westmere (microarchitecture)|Westmere microarchitecture]] [[Intel 64]] processors also support 12-bit ''process-context identifiers'' (PCIDs), which allow retaining TLB entries for multiple linear-address spaces, with only those that match the current PCID being used for address translation.<ref>{{cite web |url=https://www.realworldtech.com/westmere/ |title=Westmere Arrives |publisher=Real World Tech |author=David Kanter |date=17 March 2010 |access-date=6 January 2018}}</ref><ref>{{cite book |title=Intel 64 and IA-32 Architectures Software Developer's Manual |volume=3A: System Programming Guide, Part 1 |section=4.10.1 Process-Context Identifiers (PCIDs) |author=Intel Corporation |year=2017 |url=https://software.intel.com/sites/default/files/managed/7c/f1/253668-sdm-vol-3a.pdf#page=139}}</ref>

While selective flushing of the TLB is an option in software-managed TLBs, the only option in some hardware TLBs (for example, the TLB in the [[Intel 80386]]) is the complete flushing of the TLB on an address-space switch. Other hardware TLBs (for example, the TLB in the [[Intel 80486]] and later x86 processors, and the TLB in [[ARM architecture|ARM]] processors) allow the flushing of individual entries from the TLB indexed by virtual address.

Flushing of the TLB can be an important security mechanism for memory isolation between processes to ensure a process can't access data stored in memory pages of another process. Memory isolation is especially critical during switches between the privileged operating system kernel process and the user processes – as was highlighted by the [[Meltdown (security vulnerability)|Meltdown]] security vulnerability. Mitigation strategies such as [[kernel page-table isolation]] (KPTI) rely heavily on performance-impacting TLB flushes and benefit greatly from hardware-enabled selective TLB entry management such as PCID.<ref>{{cite web |url=https://groups.google.com/forum/m/#!topic/mechanical-sympathy/L9mHTbeQLNU |title=PCID is now a critical performance/security feature on x86 |author=Gil Tene |date=8 January 2018 |access-date=23 March 2018}}</ref>