Editing X86 memory segmentation (section)

=== 80386 protected mode ===
In the [[Intel 80386]] and later, protected mode retains the segmentation mechanism of 80286 protected mode, but a [[paging]] unit has been added as a second layer of address translation between the segmentation unit and the physical bus.  Also, importantly, address offsets are 32-bit (instead of 16-bit), and the segment base in each segment descriptor is also 32-bit (instead of 24-bit).  The general operation of the segmentation unit is otherwise unchanged.  The paging unit may be enabled or disabled; if disabled, operation is the same as on the 80286.  If the paging unit is enabled, addresses in a segment are now virtual addresses, rather than physical addresses as they were on the 80286.  That is, the segment starting address, the offset, and the final 32-bit address the segmentation unit derived by adding the two are all virtual (or logical) addresses when the paging unit is enabled.  When the segmentation unit generates and validates these 32-bit virtual addresses, the enabled paging unit finally translates these virtual addresses into physical addresses.  The physical addresses are 32-bit on the [[Intel 80386|386]], but can be larger on newer processors which support [[Physical Address Extension]].

As mentioned above, the 80386 also introduced two new general-purpose data segment registers, FS and GS, to the original set of four segment registers (CS, DS, ES, and SS).

A 386 CPU can be put back into real mode by clearing a bit in the CR0 control register, however this is a privileged operation in order to enforce security and robustness. By way of comparison, a 286 could only be returned to real mode by forcing a processor reset, e.g. by a [[triple fault]] or using external hardware.