Editing Adder (electronics) (section)

====Carry-lookahead adder (Weinberger and Smith, 1958)====

{{main|Carry-lookahead adder}}
[[File:4-bit carry lookahead adder.svg|thumb|4-bit adder with carry lookahead]]
[[File:64-bit lookahead carry unit.svg|thumb|64-bit adder with carry lookahead]]

To reduce the computation time, Weinberger and Smith invented a faster way to add two binary numbers by using [[carry-lookahead adder]]s (CLA).<ref>{{cite journal |first1=A. |last1=Weinberger |first2=J.L. |last2=Smith |title=A Logic for High-Speed Addition |journal=Nat. Bur. Stand. Circ. |issue=591 |pages=3–12 |date=1958 |publisher=National Bureau of Standards |url=https://nvlpubs.nist.gov/nistpubs/Legacy/circ/nbscircular591.pdf}}</ref> They introduced two signals (<math>P</math> and <math>G</math>) for each bit position, based on whether a carry is propagated through from a less significant bit position (at least one input is a 1), generated in that bit position (both inputs are 1), or killed in that bit position (both inputs are 0).  In most cases, <math>P</math> is simply the sum output of a half adder and <math>G</math> is the carry output of the same adder.  After <math>P</math> and <math>G</math> are generated, the carries for every bit position are created.

Mere derivation of Weinberger-Smith CLA recurrence, are: [[Brent–Kung adder]] (BKA),<ref name="Brent-Kung_1982"/> and the [[Kogge–Stone adder]] (KSA).<ref name="Kogge-Stone_1973"/><ref name="ULVD_2015"/>
This was shown in  Oklobdzija and Zeydel paper in IEEE Journal of Solid-State Circuits.<ref>{{cite journal |first1=B.R. |last1=Zeydel |first2=D. |last2=Baran |first3=V.G. |last3=Oklobdzija |title=Energy Efficient Design of High-Performance VLSI Adders |journal=IEEE Journal of Solid-State Circuits |volume=45 |issue=6 |pages=1220–33 |date=June 2010 |doi=10.1109/JSSC.2010.2048730 |url=https://www.acsel-lab.com/Publications/Papers/energy_efficient_adders.pdf}}</ref>

Some other multi-bit adder architectures break the adder into blocks.  It is possible to vary the length of these blocks based on the [[propagation delay]] of the circuits to optimize computation time.  These block based adders include the [[carry-skip adder|carry-skip (or carry-bypass) adder]] which will determine <math>P</math> and <math>G</math> values for each block rather than each bit, and the [[carry-select adder]] which pre-generates the sum and carry values for either possible carry input (0 or 1) to the block, using multiplexers to select the appropriate result ''when'' the carry bit is known.

By combining multiple carry-lookahead adders, even larger adders can be created. This can be used at multiple levels to make even larger adders. For example, the following adder is a 64-bit adder that uses four 16-bit CLAs with two levels of [[lookahead carry unit]]s.

Other adder designs include the [[carry-select adder]], [[conditional sum adder]], [[carry-skip adder]], and carry-complete adder.