Editing Consistency model (section)

=== Processor consistency ===

In order for consistency in data to be maintained and to attain scalable processor systems where every processor has its own memory, the [[processor consistency]] model was derived.<ref name=":0">{{Cite web|url=https://www-vs.informatik.uni-ulm.de/teach/ss05/dsm/arizona.pdf|title=Memory Consistency Models|access-date=2016-11-17|archive-date=2016-03-03|archive-url=https://web.archive.org/web/20160303220106/https://www-vs.informatik.uni-ulm.de/teach/ss05/dsm/arizona.pdf|url-status=dead}}</ref>  All processors need to be consistent in the order in which they see writes done by one processor and in the way they see writes by different processors to the same location (coherence is maintained). However, they do not need to be consistent when the writes are by different processors to different locations.

Every write operation can be divided into several sub-writes to all memories. A read from one such memory can happen before the write to this memory completes. Therefore, the data read can be stale. Thus, a processor under PC can execute a younger load when an older store needs to be stalled. Read before write, read after read and write before write ordering is still preserved in this model.

The processor consistency model<ref name="cacheconsistency">{{cite journal
 |  author = Goodman, James R
 |   title = Cache consistency and sequential consistency
 |    date = 1991
 | journal = IEEE Scalable Coherent Interface (SCI) Working Group
}}</ref> is similar to the [[PRAM consistency]] model with a stronger condition that defines all writes to the same memory location must be seen in the same sequential order by all other processes. Processor consistency is weaker than sequential consistency but stronger than the PRAM consistency model.

The [[Stanford DASH|Stanford DASH multiprocessor system]] implements a variation of processor consistency which is incomparable (neither weaker nor stronger) to Goodman's definitions.<ref name="senftleben13" /> All processors need to be consistent in the order in which they see writes by one processor and in the way they see writes by different processors to the same location. However, they do not need to be consistent when the writes are by different processors to different locations.