Editing Cray-1 (section)

==Cray-1S==
The '''Cray-1S''', announced in 1979, was an improved Cray-1 that supported a larger main memory of 1, 2 or 4 million words. The larger main memory was made possible through the use of 4,096 x 1-bit bipolar RAM ICs with a 25&nbsp;ns access time.<ref name="kolodzey">{{cite journal |last1=Kolodzey |first1=James S. |title=CRAY-1 Computer Technology |journal=IEEE Transactions on Components, Hybrids, and Manufacturing Technology |date=June 1981 |volume=4 |issue=2 |pages=181–186 |doi=10.1109/TCHMT.1981.1135787 |url=https://ieeexplore.ieee.org/document/1135787 |issn=1558-3082|url-access=subscription }}</ref> The Data General minicomputers were optionally replaced with an in-house 16-bit design running at 80&nbsp;MIPS. The I/O subsystem was separated from the main machine, connected to the main system via a 6&nbsp;Mbit/s control channel and a 100&nbsp;Mbit/s High Speed Data Channel. This separation made the 1S look like two "half Crays" separated by a few feet, which allowed the I/O system to be expanded as needed. Systems could be bought in a variety of configurations from the S/500 with no I/O and 0.5 million words of memory to the S/4400 with four I/O processors and 4 million words of memory.