Editing DDR SDRAM (section)

== Generations ==
DDR (DDR1) was superseded by [[DDR2 SDRAM]], which had modifications for a higher clock frequency and again doubled throughput, but operates on the same principle as DDR. Competing with DDR2 was [[Rambus]] [[XDR DRAM]]. DDR2 dominated due to cost and support factors. DDR2 was in turn superseded by [[DDR3 SDRAM]], which offered higher performance for increased bus speeds and new features. DDR3 has been superseded by [[DDR4 SDRAM]], which was first produced in 2011 and whose standards were still in flux (2012) with significant architectural changes.

DDR's prefetch buffer depth is 2 (bits), while DDR2 uses 4. Although the effective clock rates of DDR2 are higher than DDR, the overall performance was not greater in the early implementations, primarily due to the high latencies of the first DDR2 modules. DDR2 started to be effective by the end of 2004, as modules with lower latencies became available.<ref>[http://www.xbitlabs.com/articles/memory/display/ddr2-ddr.html DDR2 vs. DDR: Revenge Gained] {{webarchive|url=https://web.archive.org/web/20061121045622/http://www.xbitlabs.com/articles/memory/display/ddr2-ddr.html |date=2006-11-21 }}</ref>

Memory manufacturers stated that it was impractical to mass produce DDR1 memory with effective transfer rates in excess of 400&nbsp;MHz (i.e. 400&nbsp;MT/s and 200&nbsp;MHz external clock) due to internal speed limitations. DDR2 picks up where DDR1 leaves off, utilizing internal clock rates similar to DDR1, but is available at effective transfer rates of 400&nbsp;MHz and higher. DDR3 advances extended the ability to preserve internal clock rates while providing higher effective transfer rates by again doubling the prefetch depth.

The DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as 16 banks, 4 bank groups with 4 banks for each bank group for ×4/×8 and 8 banks, 2 bank groups with 4 banks for each bank group for ×16 DRAM.
The DDR4 SDRAM uses an 8''n'' prefetch architecture to achieve high-speed operation. The 8''n'' prefetch architecture is combined with
an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR4 SDRAM consists of a single 8''n''-bit-wide 4-clock data transfer at the internal DRAM core and 8 corresponding ''n''-bit-wide half-clock-cycle data transfers at the I/O pins.<ref>{{cite web|title=DDR4 SDRAM Standard JESD79-4B|url=https://www.jedec.org}}</ref>

[[RDRAM]] was a particularly expensive alternative to DDR SDRAM, and most manufacturers dropped its support from their chipsets. DDR1 memory's prices substantially increased from Q2 2008, while DDR2 prices declined. In January 2009, 1&nbsp;GB DDR1 was 2–3 times more expensive than 1&nbsp;GB DDR2. {{citation needed|date=December 2017}}

{| class="wikitable sortable" style="text-align: center;"
|+ {{anchor|Comparison}} Comparison of DDR SDRAM generations
! colspan="2" scope="col" | Name
! rowspan="2" scope="col" | Release<br />year
! colspan="3" scope="col" | [[Chip (computing)|Chip]]
! colspan="3" scope="col" | [[Bus (computing)|Bus]]
! rowspan="2" scope="col" | [[Voltage]]<br />(V)
! colspan="3" scope="col" | Pins
|-
! scope="col" | Gen
! scope="col" | Standard
! scope="col" | [[Clock rate]]<br />(MHz)
! scope="col" | Cycle time<br />(ns)
! scope="col" | [[Prefetch buffer|Pre-<br />fetch]]
! scope="col" | Clock rate<br />(MHz)
! scope="col" | [[Transfer (computing)|Transfer rate]]<br />([[MT/s]])
! scope="col" | [[Bandwidth (computing)|Bandwidth]]<br />(MB/s)
! scope="col" | [[DIMM]]
! scope="col" | [[SO-DIMM|SO-<br />DIMM]]
! scope="col" | [[MicroDIMM|Micro-<br />DIMM]]
|-
! rowspan="4" scope="row" | DDR
!DDR-200
| rowspan="4" | 1998
| 100
|10
| rowspan="4" | 2n
| 100
| 200
|1600
| rowspan="3" | 2.5
| rowspan="4" | 184
| rowspan="4" | 200
| rowspan="4" | 172
|-
!DDR-266
|133
|7.5
|133
|266
|{{frac|2133|1|3}}
|-
!DDR-333
|{{frac|166|2|3}}
|6
|{{frac|166|2|3}}
|333
|{{frac|2666|2|3}}
|-
!DDR-400
|200
|5
|200
|400
|3200
|2.6
|-
! rowspan="5" scope="row" |[[DDR2 SDRAM|DDR2]]
!DDR2-400
| rowspan="5" | 2003
| 100
|10
| rowspan="5" | 4n
| 200
| 400
|3200
| rowspan="5" | 1.8
| rowspan="5" | 240
| rowspan="5" | 200
| rowspan="5" | 214
|-
!DDR2-533
|{{frac|133|1|3}}
|7.5
|{{frac|266|2|3}}
|{{frac|533|1|3}}
|{{frac|4266|2|3}}
|-
!DDR2-667
|{{frac|166|2|3}}
|6
|{{frac|333|1|3}}
|{{frac|666|2|3}}
|{{frac|5333|1|3}}
|-
!DDR2-800
|200
|5
|400
|800
|6400
|-
!DDR2-1066
|{{frac|266|2|3}}
|3.75
|{{frac|533|1|3}}
|{{frac|1066|2|3}}
|{{frac|8533|1|3}}
|-
! rowspan="6" scope="row" |[[DDR3 SDRAM|DDR3]]
!DDR3-800
| rowspan="6" | 2007
| 100
|10
| rowspan="6" | 8n
| 400
| 800
|6400
| rowspan="6" | 1.5/1.35
| rowspan="6" | 240
| rowspan="6" | 204
| rowspan="6" | 214
|-
!DDR3-1066
|{{frac|133|1|3}}
|7.5
|{{frac|533|1|3}}
|{{frac|1066|2|3}}
|{{frac|8533|1|3}}
|-
!DDR3-1333
|{{frac|166|2|3}}
|6
|{{frac|666|2|3}}
|{{frac|1333|1|3}}
|{{frac|10600|2|3}}
|-
!DDR3-1600
|200
|5
|800
|1600
|12800
|-
!DDR3-1866
|{{frac|233|1|3}}
|4.29
|{{frac|933|1|3}}
|{{frac|1866|2|3}}
|{{frac|14933|1|3}}
|-
!DDR3-2133
|{{frac|266|2|3}}
|3.75
|{{frac|1066|2|3}}
|{{frac|2133|1|3}}
|{{frac|17066|2|3}}
|-
! rowspan="7" scope="row" |[[DDR4 SDRAM|DDR4]]
!DDR4-1600
| rowspan="7" | 2014
| 200
|5
| rowspan="7" | 8n
| 800
| 1600
|12800
| rowspan="7" | 1.2/1.05
| rowspan="7" | 288
| rowspan="7" | 260
| rowspan="7" |-
|-
!DDR4-1866
|{{frac|233|1|3}}
|4.29
|{{frac|933|1|3}}
|{{frac|1866|2|3}}
|{{frac|14933|1|3}}
|-
!DDR4-2133
|{{frac|266|2|3}}
|3.75
|{{frac|1066|2|3}}
|{{frac|2133|1|3}}
|{{frac|17066|2|3}}
|-
!DDR4-2400
|300
|{{frac|3|1|3}}
|1200
|2400
|19200
|-
!DDR4-2666
|{{frac|333|1|3}}
|3
|{{frac|1333|1|3}}
|{{frac|2666|2|3}}
|{{frac|21333|1|3}}
|-
!DDR4-2933
|{{frac|366|2|3}}
|2.73
|{{frac|1466|2|3}}
|{{frac|2933|1|3}}
|{{frac|23466|2|3}}
|-
!DDR4-3200
|400
|2.5
|1600
|3200
|25600
|-
! rowspan="10" |[[DDR5 SDRAM|DDR5]]
!DDR5-3200
| rowspan="10" |2020
|200
|5
| rowspan="10" |16n
|1600
|3200
|25600
| rowspan="10" |1.1
| rowspan="10" |288
| rowspan="10" |262
| rowspan="10" |
|-
!DDR5-3600
|225
|4.44
|1800
|3600
|28800
|-
!DDR5-4000
|250
|4
|2000
|4000
|32000
|-
!DDR5-4800
|300
|{{frac|3|1|3}}
|2400
|4800
|38400
|-
!DDR5-5000
|{{frac|312|1|2}}
|3.2
|2500
|5000
|40000
|-
!DDR5-5120
|320
|{{frac|3|1|8}}
|2560
|5120
|40960
|-
!DDR5-5333
|{{frac|333|1|3}}
|3
|{{frac|2666|2|3}}
|{{frac|5333|1|3}}
|{{frac|42666|2|3}}
|-
!DDR5-5600
|350
|2.86
|2800
|5600
|44800
|-
!DDR5-6400
|400
|2.5
|3200
|6400
|51200
|-
!DDR5-7200
|450
|2.22
|3600
|7200
|57600
|}

=== LPDDR ===
{{Main|LPDDR}}
LPDDR is an acronym that some enterprises use for [[LPDDR]] SDRAM, a type of memory used in some portable electronic devices, like [[mobile phone]]s, [[handheld]]s, and [[digital audio player]]s. Through techniques including reduced voltage supply and advanced refresh options, [[LPDDR]] can achieve greater power efficiency.