Editing DEC PRISM (section)

==Design==

In terms of [[integer]] operations, the PRISM architecture was similar to the [[MIPS Technologies|MIPS]] designs. Of the 32-bits in the [[instruction (computer science)|instruction]]s, the 6 highest and 5 lowest [[bit]]s were the instruction, leaving the other 21 bits of the word for encoding either a [[constant (programming)|constant]] or [[Processor register|register]] locations. Sixty-four 32-bit registers were included, as opposed to thirty-two in the MIPS, but usage was otherwise similar. PRISM and MIPS both lack the [[register window]]s that were a hallmark of the other major RISC design, Berkeley RISC.

The PRISM design was notable for several aspects of its [[instruction set]]. Notably, PRISM included '''Epicode''' (''extended processor instruction code''), which defined a number of "special" instructions intended to offer the [[operating system]] a stable [[Application Binary Interface|ABI]] across multiple implementations. Epicode was given its own set of 22 32-bit registers to use. A set of [[vector processor|vector processing]] instructions were later added as well, supported by an additional sixteen 64-bit vector registers that could be used in a variety of ways.