Editing Data General Nova (section)

===Later models===
By this time, the PDP-11 was finally shipping. It offered a much richer [[instruction set architecture]] than the deliberately simple one in the Nova. Continuing improvement in IC designs, and especially their [[price–performance ratio]], was eroding the value of the original simplified instructions. Seligman was put in charge of designing a new machine that would be compatible with the Nova while offering a much richer environment for those who wanted it. This concept shipped as the [[Data General Eclipse]] series, which offered the ability to add additional circuitry to tailor the instruction set for scientific or data processing workloads. The Eclipse was successful in competing with the PDP-11 at the higher end of the market.{{sfn|Hendrie|2002|p=58}}

Around the same time, rumors of a new 32-bit machine from DEC began to surface. DG decided they had to have a similar product, and Gruner was put in charge of what became the Fountainhead Project. Given the scope of the project, they agreed that the entire effort should be handled off-site, and Gruner selected a location at [[Research Triangle Park]] in [[North Carolina]]. This design became very complex{{sfn|Hendrie|2002|p=60}} and was ultimately canceled years later.

While these efforts were underway, work on the Nova line continued.

====840====
The 840, first offered in 1973, also included a new paged memory system allowing for addresses of up to 17-bits. An index offset the base address into the larger 128&nbsp;kword memory. Actually installing this much memory required considerable space; the 840 shipped in a large 14-slot case.

====Nova 2====
The next version was the '''Nova 2''', with the first versions shipping in 1973. The Nova 2 was essentially a simplified version of the earlier machines as increasing chip densities allowed the CPU to be reduced in size. While the SuperNOVA used three 15×15" boards to implement the CPU and its memory, the Nova 2 fitted all of this onto a single board. ROM was used to store the boot code, which was then copied into core when the "program load" switch was flipped. Versions were available with four ("2/4"), seven and ten ("2/10") slots.

====Nova 3====
[[File:Dg-nova3.jpg|thumb|right|Data General Nova 3]]
The '''Nova 3''' of 1975 added two more registers, used to control access to a built-in stack. The processor was also re-implemented using [[Transistor–transistor logic|TTL]] components, further increasing the performance of the system. The Nova 3 was offered in four-slot (the Nova 3/4) and twelve-slot (the Nova 3/12) versions.

====Nova 4====
It appears that Data General originally intended the Nova 3 to be the last of its line, planning to replace the Nova with the later Eclipse machines.{{citation needed|date=March 2024}} However, continued demand led to a '''Nova 4''' machine introduced in 1978, this time based on four [[AMD Am2901]] [[bit-slice]] [[arithmetic logic unit|ALUs]]. This machine was designed from the start to be both the Nova 4 and the Eclipse S/140, with different [[microcode]] for each. A floating-point co-processor was also available, taking up a separate slot. An additional option allowed for memory mapping, allowing programs to access up to 128&nbsp;kwords of memory using [[bank switching]]. Unlike the earlier machines, the Nova 4 did not include a [[front panel|front panel console]] and instead included a ROM containing machine code that allows a [[computer terminal|terminal]] to emulate a console when needed.<ref name="nova-4-fe-manual">{{cite book|url=http://www.bitsavers.org/pdf/dg/Nova_4/015-000095-02_Nova_4_Field_Engineering_Reference.pdf|title=Nova 4/S and 4/X|series=Field Engineer's Reference Series|date=June 1981|publisher=[[Data General]]}}</ref>{{rp|page=87}}

There were three different versions of the Nova 4, the Nova 4/C, the Nova 4/S and the Nova 4/X. The Nova 4/C was a single-board implementation that included all of the memory (16 or 32&nbsp;kwords). The Nova 4/S and 4/X used separate memory boards. The Nova 4/X had the on-board [[memory management unit]] (MMU) enabled to allow up to 128&nbsp;kwords of memory to be used. The MMU was also installed in the Nova 4/S, but was disabled by firmware. Both the 4/S and the 4/X included a "prefetcher" to increase performance by fetching up to 11 instructions from memory before they were needed.<ref name="nova-4-fe-manual" />{{rp|page=5}}