Editing Dual in-line package (section)

===Single in-line===
{{distinguish|SIPP memory}}
[[Image:SIL9 ST TDA4601.jpg|thumb|upright=1|Package sample for single in-line package (SIP or SIL) devices]]

A '''single in-line package''' ('''SIP''' or '''SIL package''')<ref>{{cite web |title=Single-in-Line Package (SIP) |url=https://eesemi.com/sip-package.htm |website=EE Semi |archive-url=https://web.archive.org/web/20210818201818/https://eesemi.com/sip-package.htm |archive-date=August 18, 2021 |url-status=live}}</ref> has one row of connecting pins. It is not as popular as the DIP, but has been used for packaging [[RAM]] chips and multiple resistors with a common pin. As compared to DIPs with a typical maximum pin count of 64, SIPs have a typical maximum pin count of 24 with lower package costs.<ref>Pecht, M. (1994). [https://books.google.com/books?id=hDwX3slSvQ4C&dq=advantages+disadvantages+single+inline+package&pg=PA48 Integrated circuit, hybrid, and multichip module package design guidelines]. Wiley-IEEE.</ref>

One variant of the single in-line package uses part of the lead frame for a heat sink tab. This [[multi-leaded power package]] is useful for such applications as audio power amplifiers, for example.