Editing Flash memory (section)

==Principles of operation==
[[File:Flash cell structure.svg|thumb|350px|right|A flash memory cell]]

Flash memory stores information in an array of memory cells made from [[floating-gate transistor]]s. In [[single-level cell]] (SLC) devices, each cell stores only one bit of information. [[Multi-level cell]] (MLC) devices, including [[triple-level cell]] (TLC) devices, can store more than one bit per cell.

The floating gate may be conductive (typically [[polycrystalline silicon|polysilicon]] in most kinds of flash memory) or non-conductive (as in [[SONOS]] flash memory).<ref>{{Citation |first=Matt |last=Basinger |title=PSoC Designer Device Selection Guide |date=18 January 2007 |id=AN2209 |url=http://www.psocdeveloper.com/uploads/tx_piapappnote/an2209_03.pdf |quote=The [[PSoC]] ... utilizes a unique Flash process: [[SONOS]] |url-status=usurped |archive-url=https://web.archive.org/web/20091031121330/http://www.psocdeveloper.com/uploads/tx_piapappnote/an2209_03.pdf |archive-date=31 October 2009}}</ref>

===Floating-gate MOSFET===
{{Main| Floating-gate MOSFET}}

In flash memory, each memory cell resembles a standard [[metal–oxide–semiconductor field-effect transistor]] (MOSFET) except that the transistor has two gates instead of one. The cells can be seen as an electrical switch in which current flows between two terminals (source and drain) and is controlled by a floating gate (FG) and a control gate (CG). The CG is similar to the gate in other MOS transistors, but below this is the FG, which is insulated all around by an oxide layer. The FG is interposed between the CG and the MOSFET channel. Because the FG is electrically isolated by its insulating layer, electrons placed on it are trapped. When the FG is charged with electrons, this charge [[electric field screening|screens]] the [[electric field]] from the CG, thus increasing the [[threshold voltage]] (V<sub>T</sub>) of the cell. This means that the V<sub>T</sub> of the cell can be changed between the ''uncharged FG threshold voltage'' (V<sub>T1</sub>) and the higher ''charged FG threshold voltage'' (V<sub>T2</sub>) by changing the FG charge. In order to read a value from the cell, an intermediate voltage (V<sub>I</sub>) between V<sub>T1</sub> and V<sub>T2</sub> is applied to the CG. If the channel conducts at V<sub>I</sub>, the FG must be uncharged (if it were charged, there would not be conduction because V<sub>I</sub> is less than V<sub>T2</sub>). If the channel does not conduct at the V<sub>I</sub>, it indicates that the FG is charged. The binary value of the cell is sensed by determining whether there is current flowing through the transistor when V<sub>I</sub> is asserted on the CG. In a multi-level cell device, which stores more than one [[bit]] per cell, the amount of current flow is sensed (rather than simply its presence or absence), in order to determine more precisely the level of charge on the FG.

Floating gate MOSFETs are so named because there is an electrically insulating tunnel oxide layer between the floating gate and the silicon, so the gate "floats" above the silicon. The oxide keeps the electrons confined to the floating gate. Degradation or wear (and the limited endurance of floating gate Flash memory) occurs due to the extremely high [[electric field]] (10 million volts per centimeter) experienced by the oxide. Such high voltage densities can break atomic bonds over time in the relatively thin oxide, gradually degrading its electrically insulating properties and allowing electrons to be trapped in and pass through freely (leak) from the floating gate into the oxide, increasing the likelihood of data loss since the electrons (the quantity of which is used to represent different charge levels, each assigned to a different combination of bits in MLC Flash) are normally in the floating gate. This is why data retention goes down and the risk of data loss increases with increasing degradation.<ref name="windbacher-211">{{Cite web |last=Windbacher |first=T. |title=2.1.1 Flash Memory |url=https://www.iue.tuwien.ac.at/phd/windbacher/node14.html |url-status=live |archive-url=https://web.archive.org/web/20231109113308/https://www.iue.tuwien.ac.at/phd/windbacher/node14.html |archive-date=9 November 2023 |website=Engineering Gate Stacks for Field-Effect Transistors }}</ref><ref name="minnesota-floating-gate-mos">{{Cite web |title=Floating Gate MOS Memory |url=http://www.princeton.edu/~chouweb/newproject/research/SEM/FloatMOSMem.html |url-status=dead |archive-url=https://web.archive.org/web/20220808223834/http://www.princeton.edu/~chouweb/newproject/research/SEM/FloatMOSMem.html |archive-date=8 August 2022 |publisher=[[University of Minnesota]] }}</ref><ref name="auto5"/><ref name="anandtech"/><ref name="electronics-notes-wear-levelling">{{Cite web |title=Flash Memory Reliability, Life & Wear |url=https://www.electronics-notes.com/articles/electronic_components/semiconductor-ic-memory/flash-wear-levelling-reliability-lifetime.php |url-status=live |archive-url=https://web.archive.org/web/20231102133652/https://www.electronics-notes.com/articles/electronic_components/semiconductor-ic-memory/flash-wear-levelling-reliability-lifetime.php |archive-date=2 November 2023 |website=Electronics Notes }}</ref> The silicon oxide in a cell degrades with every erase operation. The degradation increases the amount of negative charge in the cell over time due to trapped electrons in the oxide and negates some of the control gate voltage. Over time, this  also makes erasing the cell slower; to maintain the performance and reliability of the NAND chip, the cell must be retired from use.  Endurance also decreases with the number of bits in a cell. With more bits in a cell, the number of possible states (each represented by a different voltage level) in a cell increases and is more sensitive to the voltages used for programming. Voltages may be adjusted to compensate for degradation of the silicon oxide, and as the number of bits increases, the number of possible states also increases and thus the cell is less tolerant of adjustments to programming voltages, because there is less space between the voltage levels that define each state in a cell.<ref name="auto6">{{Cite news |last=Vättö |first=Kristian |date=23 February 2012 |title=Understanding TLC NAND |work=[[AnandTech]] |url=https://www.anandtech.com/show/5067/understanding-tlc-nand/2 |url-status=live |archive-url=https://web.archive.org/web/20231102131132/https://www.anandtech.com/show/5067/understanding-tlc-nand/2 |archive-date=2 November 2023 }}</ref>

===Fowler–Nordheim tunneling===
{{Main|Fowler–Nordheim tunneling}}

The process of moving electrons from the control gate and into the floating gate is called [[Fowler–Nordheim tunneling]], and it fundamentally changes the characteristics of the cell by increasing the MOSFET's threshold voltage. This, in turn, changes the drain-source current that flows through the transistor for a given gate voltage, which is ultimately used to encode a binary value. The Fowler-Nordheim tunneling effect is reversible, so electrons can be added to or removed from the floating gate, processes traditionally known as writing and erasing.<ref name="hyperstone-20180417">{{Cite web |date=17 April 2018 |title=Solid State bit density, and the Flash Memory Controller |url=https://www.hyperstone.com/en/Solid-State-bit-density-and-the-Flash-Memory-Controller-1235,12728.html |url-status=live |archive-url=https://web.archive.org/web/20230609075731/https://www.hyperstone.com/en/Solid-State-bit-density-and-the-Flash-Memory-Controller-1235,12728.html |archive-date=9 June 2023 |access-date=29 May 2018 |website=hyperstone.com }}</ref>

===Internal charge pumps===
Despite the need for relatively high programming and erasing voltages, virtually all flash chips today require only a single supply voltage and produce the high voltages that are required using on-chip [[charge pump]]s.

Over half the energy used by a 1.8&nbsp;V-NAND flash chip is lost in the charge pump itself. Since [[boost converter]]s are inherently more efficient than charge pumps, researchers developing [[low-power electronics|low-power]] SSDs have proposed returning to the dual Vcc/Vpp supply voltages used on all early flash chips, driving the high Vpp voltage for all flash chips in an SSD with a single shared external boost converter.<ref>{{Citation |first1=Tadashi |title=Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design - ISLPED '09 |last1=Yasufuku |first2=Koichi |last2=Ishida |first3=Shinji |last3=Miyamoto |first4=Hiroto |last4=Nakai |first5=Makoto |last5=Takamiya |first6=Takayasu |last6=Sakurai |first7=Ken |last7=Takeuchi |journal=IEICE Transactions on Electronics |url=http://www.computer.org/csdl/proceedings/islped/2009/8684/00/86840087-abs.html |pages=87–92 |year=2009 |volume=93 |issue=3 |url-status=live |archive-url=https://web.archive.org/web/20160305135918/https://www.computer.org/csdl/proceedings/islped/2009/8684/00/86840087-abs.html |archive-date=5 March 2016|doi=10.1145/1594233.1594253 |isbn=9781605586847 |s2cid=6055676 |url-access=subscription |bibcode=2010IEITE..93..317Y}}</ref><ref>{{citation |first1=Rino |last1=Micheloni |first2=Alessia |last2=Marelli |first3=Kam |last3=Eshghi |url=https://books.google.com/books?id=8LS3egzcBG4C&pg=PA188 |title=Inside Solid State Drives (SSDs) |year=2012 |publisher=Springer |url-status=live |archive-url=https://web.archive.org/web/20170209234319/https://books.google.com/books?id=8LS3egzcBG4C&pg=PA188&lpg=PA188 |archive-date=9 February 2017|isbn=9789400751460 |bibcode=2013issd.book.....M }}</ref><ref>{{citation |first1=Rino |last1=Micheloni |first2=Luca |last2=Crippa |url=https://books.google.com/books?id=vaq11vKwo_kC&pg=PA530 |title=Inside NAND Flash Memories |year=2010 |publisher=Springer |url-status=live |archive-url=https://web.archive.org/web/20170209164808/https://books.google.com/books?id=vaq11vKwo_kC&pg=PA530&lpg=PA530 |archive-date=9 February 2017|isbn=9789048194315 }} In particular, {{cite book |doi=10.1007/978-90-481-9431-5_18 |chapter=Low power 3D-integrated SSD |title=Inside NAND Flash Memories |date=2010 |last1=Takeuchi |first1=K. |pages=515–536 |isbn=978-90-481-9430-8 }}</ref><ref>{{citation |first1=Tracey |last1=Mozel |url=https://books.google.com/books?id=XlbOf-m8fdYC&pg=RA5-PA3 |title=CMOSET Fall 2009 Circuits and Memories Track Presentation Slides |year=2009 |publisher=CMOS Emerging Technologies |url-status=live |archive-url=https://web.archive.org/web/20170209213305/https://books.google.com/books?id=XlbOf-m8fdYC&pg=RA5-PA3&lpg=RA5-PA3 |archive-date=9 February 2017|isbn=9781927500217 }}</ref><ref name="ieice-transactions-2010">{{Cite journal |last1=Yasufuku |first1=Tadashi |last2=Ishida |first2=Koichi |last3=Miyamoto |first3=Shinji |last4=Nakai |first4=Hiroto |last5=Takamiya |first5=Makoto |last6=Sakurai |first6=Takayasu |last7=Takeuchi |first7=Ken |date=March 2010 |title=Inductor and TSV Design of 20-V Boost Converter for Low Power 3D Solid State Drive with NAND Flash Memories |pages=317–323 |url=https://www.researchgate.net/publication/220240029  |url-status=live |journal=IEICE Transactions on Electronics |publisher=[[Institute of Electronics, Information and Communication Engineers|IEICE]] |volume=E93-C |issue=3 |doi=10.1587/transele.E93.C.317 |archive-url=https://web.archive.org/web/20160204025034/https://www.researchgate.net/publication/220240029_Inductor_and_TSV_Design_of_20-V_Boost_Converter_for_Low_Power_3D_Solid_State_Drive_with_NAND_Flash_Memories |archive-date=4 February 2016 |doi-access= |bibcode=2010IEITE..93..317Y |url-access=subscription }}</ref><ref>{{cite web | url=https://ieeexplore.ieee.org/document/5986104 | title=4-times faster rising VPASS (10V), 15% lower power VPGM (20V), wide output voltage range voltage generator system for 4-times faster 3D-integrated solid-state drives | date=June 2011 | pages=200–201 }}</ref><ref name="takeuchi-2010">{{Cite conference |last=Takeuchi |first=Ken |date=May 2010 |title=Low power 3D-integrated Solid-State Drive (SSD) with adaptive voltage generator |conference=IEEE International Memory Workshop (IMW)  |location=Seoul, Korea |doi=10.1109/IMW.2010.5488397 |isbn=978-1-4244-6721-1 |issn=2159-4864 }}</ref><ref name="ieee-3d-integrated-2011">{{Cite journal |last1=Ishida |first1=Koichi |last2=Yasufuku |first2=Tadashi |last3=Miyamoto |first3=Shinji |last4=Nakai |first4=Hiroto |last5=Takamiya |first5=Makoto |last6=Sakurai |first6=Takayasu |last7=Takeuchi |first7=Ken |date=May 2011 |title=1.8 V Low-Transient-Energy Adaptive Program-Voltage Generator Based on Boost Converter for 3D-Integrated NAND Flash SSD |journal=IEEE Journal of Solid-State Circuits |publisher=[[Institute of Electrical and Electronics Engineers]] |volume=46 |issue=6 |pages=1478–1487 |doi=10.1109/JSSC.2011.2131810 |bibcode=2011IJSSC..46.1478I |s2cid=13701601 |issn=1558-173X }}</ref>

In spacecraft and other high-radiation environments, the on-chip charge pump is the first part of the flash chip to fail, although flash memories will continue to work{{snd}} in read-only mode{{snd}} at much higher radiation levels.<ref>A. H. Johnston, [http://trs-new.jpl.nasa.gov/dspace/bitstream/2014/13431/1/01-2369.pdf "Space Radiation Effects in Advanced Flash Memories"] {{webarchive|url=https://web.archive.org/web/20160304220536/http://trs-new.jpl.nasa.gov/dspace/bitstream/2014/13431/1/01-2369.pdf |date=4 March 2016 }}.
NASA Electronic Parts and Packaging Program (NEPP). 2001. "... internal transistors used for the charge pump and erase/write control have much thicker oxides because of the requirement for high voltage. This causes flash devices to be considerably more sensitive to total dose damage compared to other [[ULSI]] technologies. It also implies that write and erase functions will be the first parameters to fail from total dose. ... Flash memories will work at much higher radiation levels in the read mode. ... The charge pumps that are required to generate the high voltage for erasing and writing are usually the most sensitive circuit functions, usually failing below 10 [[kilorad|krad]](SI)."</ref>

===NOR flash===
[[File:NOR flash layout.svg|thumb|350px|right| NOR flash memory wiring and structure on silicon]]

In NOR flash, each cell has one end connected directly to ground, and the other end connected directly to a bit line. This arrangement is called "NOR flash" because it acts like a [[NOR gate|NOR&nbsp;gate;]]  when one of the word lines (connected to the cell's CG) is brought high, the corresponding storage transistor acts to pull the output bit line low. NOR flash continues to be the technology of choice for embedded applications requiring a discrete non-volatile memory device.{{citation needed|date=May 2022}} The low read latencies characteristic of NOR&nbsp;devices allow for both direct code execution and data storage in a single memory product.<ref name="eetimes-20110502">{{Cite news |last=Zitlaw |first=Cliff |date=2 May 2011 |title=The Future of NOR Flash Memory |work=Memory Designline |publisher=UBM Media |url=https://www.eetimes.com/the-future-of-nor-flash-memory/ |url-status=live |access-date=3 May 2011 |archive-url=https://web.archive.org/web/20230601001439/https://www.eetimes.com/the-future-of-nor-flash-memory/ |archive-date=1 June 2023 }}</ref>

====Programming====
[[Image:Flash-Programming.svg|thumb|left|Programming a NOR memory cell (setting it to logical 0), via hot-electron injection]]
[[File:Flash erase.svg|thumb|right|Erasing a NOR memory cell (setting it to logical 1), via quantum tunneling]]

A single-level NOR flash cell in its default state is logically equivalent to a binary "1" value, because current will flow through the channel under application of an appropriate voltage to the control gate, so that the bitline voltage is pulled down. A NOR&nbsp;flash cell can be programmed, or set to a binary "0" value, by the following procedure:

* an elevated on-voltage (typically >5&nbsp;V) is applied to the CG
* the channel is now turned on, so electrons can flow from the source to the drain (assuming an NMOS&nbsp;transistor)
* the source-drain current is sufficiently high to cause some high energy electrons to jump through the insulating layer onto the FG, via a process called [[hot carrier injection|hot-electron injection]].

====Erasing====
To erase a NOR flash cell (resetting it to the "1" state), a large voltage ''of the opposite polarity'' is applied between the CG and source terminal, pulling the electrons off the FG through [[Fowler–Nordheim tunneling]] (FN tunneling).<ref>{{cite book | url=https://books.google.com/books?id=44mbEAAAQBAJ&dq=nor+flash+erase&pg=PA55 | isbn=978-3-030-79827-7 | title=Springer Handbook of Semiconductor Devices | date=10 November 2022 | publisher=Springer }}</ref> This is known as Negative gate source source erase. Newer NOR memories can erase using negative gate channel erase, which biases the wordline on a NOR memory cell block and the P-well of the memory cell block to allow FN tunneling to be carried out, erasing the cell block. Older memories used source erase, in which a high voltage was applied to the source and then electrons from the FG were moved to the source.<ref>{{cite book | url=https://books.google.com/books?id=2E0r6BRo2VkC&dq=nor+flash+erase&pg=PA212 | isbn=978-90-481-9216-8 | title=CMOS Processors and Memories | date=9 August 2010 | publisher=Springer }}</ref><ref>{{cite journal | url=https://ieeexplore.ieee.org/document/1035946 | title=  High-voltage transistor scaling circuit techniques for high-density negative-gate channel-erasing NOR flash memories| date= 2002| doi=10.1109/JSSC.2002.803045 | last1= Tanzawa| first1= T.| last2= Takano| first2= Y.| last3= Watanabe| first3= K.| last4= Atsumi| first4= S.| journal= IEEE Journal of Solid-State Circuits| volume= 37| issue= 10| pages= 1318–1325| bibcode= 2002IJSSC..37.1318T| url-access= subscription}}</ref> Modern NOR&nbsp;flash memory chips are divided into erase segments (often called blocks or sectors). The erase operation can be performed only on a block-wise basis; all the cells in an erase segment must be erased together.<ref>{{cite book | url=https://books.google.com/books?id=abfBAAAAQBAJ&dq=nor+erase+block&pg=PA41 | isbn=978-94-007-6082-0 | title=Flash Memories: Economic Principles of Performance, Cost and Reliability Optimization | date=12 September 2013 | publisher=Springer }}</ref> Programming of NOR cells, however, generally can be performed one byte or word at a time.

{{clear}}
[[File:Nand flash structure.svg|thumb|350px|right|NAND flash memory wiring and structure on silicon]]

===NAND flash===
NAND flash also uses [[Floating-gate MOSFET|floating-gate transistor]]s, but they are connected in a way that resembles a [[NAND&nbsp;gate]]: several transistors are connected in series, and the bit line is pulled low only if all the word lines are pulled high (above the transistors' V<sub>T</sub>). These groups are then connected via some additional transistors to a NOR-style bit line array in the same way that single transistors are linked in NOR&nbsp;flash.

Compared to NOR flash, replacing single transistors with serial-linked groups adds an extra level of addressing. Whereas NOR&nbsp;flash might address memory by page then word, NAND&nbsp;flash might address it by page, word and bit. Bit-level addressing suits bit-serial applications (such as hard disk emulation), which access only one bit at a time. {{nowrap|Execute-in-place}} applications, on the other hand, require every bit in a word to be accessed simultaneously. This requires word-level addressing. In any case, both bit and word addressing modes are possible with either NOR or NAND&nbsp;flash.

To read data, first the desired group is selected (in the same way that a single transistor is selected from a NOR array). Next, most of the word lines are pulled up above V<sub>T2</sub>, while one of them is pulled up to V<sub>I</sub>. The series group will conduct (and pull the bit line low) if the selected bit has not been programmed.

Despite the additional transistors, the reduction in ground wires and bit lines allows a denser layout and greater storage capacity per chip. (The ground wires and bit lines are actually much wider than the lines in the diagrams.) In addition, NAND&nbsp;flash is typically permitted to contain a certain number of faults (NOR&nbsp;flash, as is used for a [[BIOS]]&nbsp;ROM, is expected to be fault-free). Manufacturers try to maximize the amount of usable storage by shrinking the size of the transistors or cells, however the industry can avoid this and achieve higher storage densities per die by using 3D NAND, which stacks cells on top of each other.

NAND flash cells are read by analysing their response to various voltages.<ref name="anandtech">{{Cite news |last=Shimpi |first=Anand Lal |date=30 September 2011 |title=The Intel SSD 710 (200GB) Review |work=[[AnandTech]] |url=https://www.anandtech.com/show/4902/intel-ssd-710-200gb-review |url-status=live |archive-url=https://web.archive.org/web/20231102131301/https://www.anandtech.com/show/4902/intel-ssd-710-200gb-review |archive-date=2 November 2023 }}</ref>

====Writing and erasing====
NAND flash uses [[tunnel injection]] for writing and [[tunnel release]] for erasing. NAND&nbsp;flash memory forms the core of the removable [[Universal Serial Bus|USB]] storage devices known as [[USB flash drive]]s, as well as most [[memory card]] formats and [[solid-state drive]]s available today.

The hierarchical structure of NAND flash starts at a cell level which establishes strings, then pages, blocks, planes and ultimately a die. A string is a series of connected NAND cells in which the source of one cell is connected to the drain of the next one. Depending on the NAND technology, a string typically consists of 32 to 128 NAND cells. Strings are organised into pages which are then organised into blocks in which each string is connected to a separate line called a bitline. All cells with the same position in the string are connected through the control gates by a wordline. A plane contains a certain number of blocks that are connected through the same bitline. A flash die consists of one or more planes, and the peripheral circuitry that is needed to perform all the read, write, and erase operations.

The architecture of NAND flash means that data can be read and programmed (written) in pages, typically between 4 KiB and 16 KiB in size, but can only be erased at the level of entire blocks consisting of multiple pages. When a block is erased, all the cells are logically set to 1. Data can only be programmed in one pass to a page in a block that was erased. The programming process is set one or more cells from 1 to 0. Any cells that have been set to 0 by programming can only be reset to 1 by erasing the entire block. This means that before new data can be programmed into a page that already contains data, the current contents of the page plus the new data must all be copied to a new, erased page. If a suitable erased page is available, the data can be written to it immediately. If no erased page is available, a block must be erased before copying the data to a page in that block. The old page is then marked as invalid and is available for erasing and reuse.<ref name="hyperstone-20180607">{{Cite web |date=7 June 2018 |title=NAND Flash Controllers - The key to endurance and reliability |url=https://www.hyperstone.com/en/NAND-Flash-controllers-The-key-to-endurance-and-reliability-1256,12728.html |url-status=live |archive-url=https://web.archive.org/web/20230605095907/https://www.hyperstone.com/en/NAND-Flash-controllers-The-key-to-endurance-and-reliability-1256,12728.html |archive-date=5 June 2023 |access-date=1 June 2022 |work=hyperstone.com }}</ref> This is different from operating system [[logical block addressing|LBA]] view, for example, if operating system writes 1100 0011 to the flash storage device (such as [[SSD]]), the data actually written to the flash memory may be 0011 1100.

===Vertical NAND===
[[File:NAND_Flash_Bit_Cost_from_2D_to_3D.png|thumb|right|300px|3D NAND continues scaling beyond 2D.]]
Vertical NAND (V-NAND) or 3D NAND memory stacks memory cells vertically and uses a [[charge trap flash]] architecture. The vertical layers allow larger areal bit densities without requiring smaller individual cells.<ref name="vnand">{{cite web |url=http://www.gizmag.com/samsung-v-nand-flash-chip-ssd/28655 |title=Samsung moves into mass production of 3D flash memory |publisher=Gizmag.com |access-date=2013-08-27 |url-status=live |archive-url=https://web.archive.org/web/20130827091835/http://www.gizmag.com/samsung-v-nand-flash-chip-ssd/28655/ |archive-date=27 August 2013|date=27 August 2013 }}</ref> It is also sold under the trademark ''BiCS Flash'', which is a trademark of Kioxia Corporation (formerly Toshiba Memory Corporation). 3D NAND was first announced by [[Toshiba]] in 2007.<ref name="toshiba-3d">{{Cite news |last=Melanson |first=Donald |date=12 June 2007 |title=Toshiba announces new "3D" NAND flash technology |work=[[Engadget]] |url=https://www.engadget.com/2007/06/12/toshiba-announces-new-3d-nand-flash-technology/ |url-status=live |access-date=10 July 2019 |archive-url=https://web.archive.org/web/20221217224115/https://www.engadget.com/2007-06-12-toshiba-announces-new-3d-nand-flash-technology.html |archive-date=17 December 2022 }}</ref> V-NAND was first commercially manufactured by [[Samsung Electronics]] in 2013.<ref name="samsung-3d">{{Cite press release |date=13 August 2013 |title=Samsung Introduces World's First 3D V-NAND Based SSD for Enterprise Applications |url=https://www.samsung.com/semiconductor/insights/news-events/samsung-introduces-worlds-first-3d-v-nand-based-ssd-for-enterprise-applications/ |url-status=dead |archive-url=https://web.archive.org/web/20190414192036/https://www.samsung.com/semiconductor/insights/news-events/samsung-introduces-worlds-first-3d-v-nand-based-ssd-for-enterprise-applications/ |archive-date=14 April 2019 |publisher=[[Samsung]] }}</ref><ref name="samsung-3d-ee">{{Cite news |last=Clarke |first=Peter |date=8 August 2013 |title=Samsung Confirms 24 Layers in 3D NAND |work=[[EE Times]] |url=https://www.eetimes.com/samsung-confirms-24-layers-in-3d-nand/ |url-status=live |archive-url=https://web.archive.org/web/20200219151255/https://www.eetimes.com/samsung-confirms-24-layers-in-3d-nand/ |archive-date=19 February 2020 }}</ref><ref name="samsung-20141009">{{Cite press release |date=9 October 2014 |title=Samsung Electronics Starts Mass Production of Industry First 3-bit 3D V-NAND Flash Memory |url=https://news.samsung.com/global/samsung-electronics-starts-mass-production-of-industry-first-3-bit-3d-v-nand-flash-memory |url-status=live |archive-url=https://web.archive.org/web/20230330135736/https://news.samsung.com/global/samsung-electronics-starts-mass-production-of-industry-first-3-bit-3d-v-nand-flash-memory |archive-date=30 March 2023 |publisher=[[Samsung]] }}</ref><ref name="samsung-vnand-2014">{{Cite web |date=September 2014 |title=Samsung V-NAND technology |url=http://www.samsung.com/us/business/oem-solutions/pdfs/V-NAND_technology_WP.pdf |url-status=dead |archive-url=https://web.archive.org/web/20160327194431/http://www.samsung.com/us/business/oem-solutions/pdfs/V-NAND_technology_WP.pdf |archive-date=27 March 2016 |access-date=27 March 2016 |publisher=[[Samsung]] }}</ref>

====Structure====
V-NAND uses a [[charge trap flash]] geometry (which was commercially introduced in 2002 by [[AMD]] and [[Fujitsu]])<ref name="auto3"/> that stores charge on an embedded [[silicon nitride]] film. Such a film is more robust against point defects and can be made thicker to hold larger numbers of electrons. V-NAND wraps a planar charge trap cell into a cylindrical form.<ref name="vnand" /> As of 2020, 3D NAND flash memories by Micron and Intel instead use floating gates, however, Micron 128 layer and above 3D NAND memories use a conventional charge trap structure, due to the dissolution of the partnership between Micron and Intel. Charge trap 3D NAND flash is thinner than floating gate 3D NAND. In floating gate 3D NAND, the memory cells are completely separated from one another, whereas in charge trap 3D NAND, vertical groups of memory cells share the same silicon nitride material.<ref name="anandtech-20201109">{{Cite news |last=Tallis |first=Billy |date=9 November 2020 |title=Micron Announces 176-layer 3D NAND |work=[[AnandTech]] |url=https://www.anandtech.com/show/16230/micron-announces-176layer-3d-nand |url-status=live |archive-url=https://web.archive.org/web/20231102133017/https://www.anandtech.com/show/16230/micron-announces-176layer-3d-nand |archive-date=2 November 2023 }}</ref> <!--the exact details of the V-NAND structure vary by manufacturer.-->

An individual memory cell is made up of one planar polysilicon layer containing a hole filled by multiple concentric vertical cylinders. The hole's polysilicon surface acts as the gate electrode. The outermost silicon dioxide cylinder acts as the gate dielectric, enclosing a silicon nitride cylinder that stores charge, in turn enclosing a silicon dioxide cylinder as the tunnel dielectric that surrounds a central rod of conducting polysilicon which acts as the conducting channel.<ref name="vnand" />

Memory cells in different vertical layers do not interfere with each other, as the charges cannot move vertically through the silicon nitride storage medium, and the electric fields associated with the gates are closely confined within each layer. The vertical collection is electrically identical to the serial-linked groups in which conventional NAND&nbsp;flash memory is configured.<ref name="vnand" /> There is also string stacking, which builds several 3D NAND memory arrays or "plugs"<ref>{{Cite web|url=https://blocksandfiles.com/2023/08/18/samsung-has-300-layer-nand-coming-with-430-layers-after-that/|title=Samsung has 300-layer NAND coming, with 430 layers after that – report|first=Chris|last=Mellor|date=18 August 2023}}</ref> separately, but stacked together to create a product with a higher number of 3D NAND layers on a single die. Often, two or 3 arrays are stacked. The misalignment between plugs is in the order of 30 to 10nm.<ref name="auto8"/><ref>{{Cite book|chapter-url=https://ieeexplore.ieee.org/document/9282426|title=2020 China Semiconductor Technology International Conference (CSTIC)|doi=10.1109/CSTIC49141.2020.9282426 |chapter=Manufacturing Challenges and Cost Evaluation of New Generation 3D Memories |date=2020 |last1=Dube |first1=Belinda Langelihle |pages=1–3 |isbn=978-1-7281-6558-5 |s2cid=229376195 }}</ref><ref name="auto9">{{Cite web |last=Choe |first=Jeongdong |date=2019 |title=Comparison of Current 3D NAND Chip & Cell Architecture |url=https://files.futurememorystorage.com/proceedings/2019/08-07-Wednesday/20190807_FTEC-202-1_Choe.pdf |pages=21, 24}}</ref>

====Construction====
Growth of a group of V-NAND cells begins with an alternating stack of conducting (doped) polysilicon layers and insulating silicon dioxide layers.<ref name="vnand" />

The next step is to form a cylindrical hole through these layers. In practice, a 128&nbsp;[[Gbit]] V-NAND chip with 24 layers of memory cells requires about 2.9 billion such holes. Next, the hole's inner surface receives multiple coatings, first silicon dioxide, then silicon nitride, then a second layer of silicon dioxide. Finally, the hole is filled with conducting (doped) polysilicon.<ref name="vnand" />

====Performance====
{{As of|2013|post=,}} V-NAND flash architecture allows read and write operations twice as fast as conventional NAND and can last up to 10 times as long, while consuming 50 percent less power. They offer comparable physical bit density using 10-nm lithography but may be able to increase bit density by up to two orders of magnitude, given V-NAND's use of up to several hundred layers.<ref name="vnand" /> As of 2020, V-NAND chips with 160 layers are under development by Samsung.<ref name="techspot-20200420">{{Cite news |last=Potoroaca |first=Adrian |date=20 April 2020 |title=Samsung said to be developing industry's first 160-layer NAND flash memory chip |work=TechSpot |url=https://www.techspot.com/news/84905-samsung-developing-industry-first-160-layer-nand-flash.html |url-status=live |archive-url=https://web.archive.org/web/20231102130037/https://www.techspot.com/news/84905-samsung-developing-industry-first-160-layer-nand-flash.html |archive-date=2 November 2023 }}</ref> As the number of layers increases, the capacity and endurance of flash memory may be increased.

====Cost====
[[File:3D NAND minimum cost example.png|thumb|right|300px|'''Minimum bit cost of 3D NAND from non-vertical sidewall.''' The top opening widens with more layers, counteracting the increase in bit density.]]
The wafer cost of a 3D NAND is comparable with scaled down (32&nbsp;nm or less) planar NAND flash.<ref>{{cite web|url=https://www.linkedin.com/pulse/toshibas-cost-model-3d-nand-frederick-chen|title=Toshiba's Cost Model for 3D NAND|website=www.linkedin.com}}</ref> However, with planar NAND scaling stopping at 16&nbsp;nm, the cost per bit reduction can continue by 3D NAND starting with 16 layers. However, due to the non-vertical sidewall of the hole etched through the layers; even a slight deviation leads to a minimum bit cost, i.e., minimum equivalent design rule (or maximum density), for a given number of layers; this minimum bit cost layer number decreases for smaller hole diameter.<ref>{{cite web |title=Calculating the Maximum Density and Equivalent 2D Design Rule of 3D NAND Flash |url=https://www.linkedin.com/pulse/calculating-maximum-density-equivalent-2d-design-rule-frederick-chen |website=linkedin.com |access-date=1 June 2022}}; {{cite web |url=https://semiwiki.com/lithography/296121-calculating-the-maximum-density-and-equivalent-2d-design-rule-of-3d-nand-flash/ |title=Calculating the Maximum Density and Equivalent 2D Design Rule of 3D NAND Flash |website=semwiki.com |access-date=1 June 2022}}</ref>